Philips Semiconductors RF Communications Products
Product specification
Divide by: 64/65/72 triple modulus low power
ECL prescaler
SA702
DESCRIPTION
The SA702 triple modulus (Divide By
64/65/72) low power ECL prescaler is used in
synthesizer systems to achieve low phase
lock time, broad operating range, high
reference frequency and small frequency
step sizes. The minimum supply voltage is
2.7V and is compatible with the CMOS
UMA1005 synthesizer from Philips and other
logic circuits. The low supply current allows
application in battery operated low-power
equipment. Maximum input signal frequency
is 1.1GHz for cellular and other land mobile
applications. There is no lower frequency
limit due to a fully static design. The circuit is
implemented in ECL technology on the
QUBiC process. The circuit will be available
in an 8-pin SO package with 150 mil package
width and in 8-pin dual in-line plastic
package.
FEATURES
•
Low voltage operation
•
Low current consumption
•
Operation up to 1.1GHz
•
ESD hardened
APPLICATIONS
PIN CONFIGURATION
N, D Package
1
2
3
4
8
7
6
5
IN
GND
MC1
OUT
IN
V
C
C
MC2
OUT
•
Cellular phones
•
Cordless phones
•
RF LANs
•
Test and measurement
•
Military radio
•
VHF/UHF mobile radio
•
VHF/UHF hand-held radio
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
8-Pin Plastic Small Outline (SO) package (Surface-mount)
TEMPERATURE RANGE
-40 to +85°C
-40 to +85°C
ORDER CODE
SA702N
SA702D
DWG #
0404B
0174C
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
V
IN
I
O
T
STG
T
A
θ
JA
Supply voltage
Voltage applied to any other pin
Output current
Storage temperature range
Operating ambient temperature range
Thermal impedance
D package
N package
PARAMETER
RATING
-0.3 to +7.0
-0.3 to (V
CC
+ 0.3)
10
-65 to +125
-55 to +125
158
108
UNITS
V
V
mA
°C
°C
°C/W
June 17, 1993
2
853-1709 10044
Philips Semiconductors RF Communications Products
Product specification
Divide by: 64/65/72 triple modulus low power
ECL prescaler
SA702
DC ELECTRICAL CHARACTERISTICS
SYMBOL
V
CC
I
CC
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
PARAMETER
Power supply voltage range
Supply current
Output high level
Output low level
MC1 input high threshold
MC1 input low threshold
MC2 input high threshold
MC2 input low threshold
MC1 input high current
MC1 input low current
MC2 input high current
MC2 input low current
The following DC specifications are valid for T
A
= 25
°
C and V
CC
= 3.0V; unless otherwise stated. Test circuit Figure 1.
TEST CONDITIONS
MIN
f
IN
= 1GHz, input level = 0dBm
No load
I
OUT
= 1.2mA
V
CC
-1.4
V
CC
-2.6
2.0
–0.3
2.0
–0.3
V
MC1
= V
CC
= 6V
V
MC1
= 0V, V
CC
= 6V
V
MC2
= V
CC
= 6V
V
MC2
= 0V, V
CC
= 6V
–100
–100
0.1
–30
0.1
–30
50
V
CC
0.8
V
CC
0.8
50
2.7
4.5
LIMITS
TYP
MAX
6.0
V
mA
V
V
V
V
V
V
µA
µA
µA
µA
UNITS
AC ELECTRICAL CHARACTERISTICS
SYMBOL
V
IN
f
IN
R
ID
V
O
t
S
t
H
t
PD
Input signal
PARAMETER
amplitude
1
These AC specifications are valid for f
IN
= 1GHz, input level = 0dBm, V
CC
= 3.0V and T
A
= 25
°
C; unless otherwise stated. Test circuit Fig. 1.
TEST CONDITIONS
MIN
1000pF input coupling
Direct coupled input
2
1000pF input coupling
Differential input resistance
Output voltage
Modulus set-up
time
1
10
DC measurement
V
CC
= 5.0V
V
CC
= 3.0V
Modulus hold time
1
Propagation time
5
1.6
1.2
5
0
0.05
0
Input signal frequency
LIMITS
TYP
MAX
2.0
1.1
1.1
V
P-P
GHz
GHz
kΩ
V
P-P
V
P-P
ns
ns
ns
UNITS
NOTES:
1. Maximum limit is not tested, however, it is guaranteed by design and characterization.
2. For f
IN
< 50MHz, minimum input slew rate of 32V/µs is required.
DESCRIPTION OF OPERATION
The SA702 comprises a frequency divider
circuit implemented using a divide by 4 or 5
synchronous prescaler followed by a 5 stage
synchronous counter, see BLOCK
DIAGRAM. The normal operating mode is for
MC1 (Modulus Control) to be set high and
MC2 input to be set low in which case the
circuit comprises a divide by 64. For divide
by 65 the MC1 singal is forced low, causing
the prescaler circuit to switch into divide by 5
operation for the last cycle of the
synchronous counter. For divide by 72, MC2
is set high configuring the prescaler to divide
by 4 and the counter to divide by 18. A truth
table for the modulus values is given below:
Table 1.
Modulus
64
65
72
72
MC1
1
0
0
1
MC2
0
0
1
1
reduced input current. CMOS and low
voltage interface capability are allowed.
The prescaler input is differential and ECL
compatible. The output is differential ECL
compatible.
For minimization of propagation delay effects,
the second divider circuit is synchronous to
the divide by 4/5 stage output.
The prescaler input is positive edge sensitive,
and the output at the final count is a falling
edge with propagation delay t
PD
relative to
the input. The rising edge of the output
occurs at the count 32 with delay t
PD
.
The MC1 and MC2 inputs are TTL
compatible threshold inputs operating at a
June 17, 1993
4
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