K4R881869M
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 288Mbit Direct Rambus DRAMs (RDRAM®) are
extremely high-speed CMOS DRAMs organized as 16M
words by 18 bits. The use of Rambus Signaling Level (RSL)
technology permits 600MHz to 800MHz transfer rates while
using conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data trans-
fers at 1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage/band-
width or for error correction.
Preliminary
Direct RDRAM
™
SAMSUNG 001
K4R88xx69A-Nxxx
Figure 1: Direct RDRAM CSP Package
Key Timing Parameters/Part Numbers
Speed
Organization
Bin
512Kx18x32s
a
-CG6
-CK7
-CK8
I/O
Freq.
MHz
600
711
800
t
RAC
(Row
Access
Time) ns
53.3
45
45
Part Number
K4R881869M-N
b
C
c
G6
K4R881869M-NCK7
K4R881869M-NCK8
Features
♦Highest
sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control/data buses for maximum efficiency
- Separate row and column control buses for easy
scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦Low
latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦Advanced
power management:
- Multiple low power states allows flexibility in power
consumption versus time to active state
- Power-down self-refresh
♦Organization:
2Kbyte pages and 32 banks, x 18
- x18 organization allows ECC configurations or
increased storage and bandwidth
♦Used
Rambus Signaling Level (RSL) for up to 800MHz oper-
ation
a.The
“32s”
designation indicates that this RDRAM core is composed of 32
banks which use a
“split”
bank architecture.
b.The
“N”
designator indicates the normal package
c.The
“C”
designator indicates that this RDRAM core uses Normal Power
Self Refresh.
The 288Mbit Direct RDRAMs are offered in a CSP hori-
zontal package suitable for desktop as well as low-profile
add-in card and mobile applications.
Page 1
Rev. 0.9 Jan. 2000
K4R881869M
Preliminary
Direct RDRAM
™
Table 2: Pin Description
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
a
# Pins
2
Description
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
Serial clock input. Clock source used for reading from and writing to
the control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
Row access control. Three pins containing control and address
information for row accesses.
Column access control. Five pins containing control and address
information for column accesses.
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM.
CMD
I
CMOS
a
1
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
I
CMOS
a
1
24
1
2
28
2
I/O
I
I
RSL
b
RSL
b
RSL
b
9
1
1
1
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
9
92
Total pin count per package
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Rev. 0.9 Jan. 2000
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