Philips Semiconductors
Product specification
RF dual gain-stage
SA5200
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
P
D
T
JMAX
P
MAX
T
STG
Supply voltage
1
Power dissipation, T
A
= 25°C (still air)
2
8-Pin Plastic SO
Maximum operating junction temperature
Maximum power input/output
Storage temperature range
PARAMETER
RATING
-0.5 to +9
780
150
+20
–65 to +150
UNITS
V
mW
°C
dBm
°C
NOTE:
1. Transients exceeding 10.5V on V
CC
pin may damage product.
2. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance,
θ
JA
:
8-Pin SO:
θ
JA
= 158°C/W
DC ELECTRICAL CHARACTERISTICS
V
CC
= +5V, T
A
= 25°C; unless otherwise stated.
SYMBOL
V
CC
I
CC
Supply voltage
V
CC
= 5V, ENABLE = High
Total supply current
V
CC
= 5V, ENABLE = Low
V
CC
= 9V, ENABLE = High
V
CC
= 9V, ENABLE = Low
V
T
V
IH
V
IL
I
IL
I
IH
V
IDC,ODC
TTL/CMOS logic threshold voltage
1
Logic 1 level
Logic 0 level
Enable input current
Enable input current
Input and output DC levels
Power-up mode
Power-down mode
Enable = 0.4V
Enable = 2.4V
2.0
-0.3
-1
-1
0.6
0
0
0.83
PARAMETER
TEST CONDITIONS
LIMITS
MIN
4
6.4
TYP
5.0
8.4
95
17.8
320
1.25
V
CC
0.8
1
1
1.0
MAX
9.0
10.4
255
22.2
960
UNITS
V
mA
µA
mA
µA
V
V
V
µA
µA
V
NOTE:
1. The ENABLE input must be connected to a valid logic level for proper operation of the SA5200.
AC ELECTRICAL CHARACTERISTICS
1
V
CC
= +5V, T
A
= 25
°
C, either amplifier, enable = 5V; unless otherwise stated.
SYMBOL
S21
S22
S12
S11
P-1
NF
IP
2
IP
3
ISOL
P
OUT
S21
Insertion gain
Output return loss
Reverse isolation
Input return loss
Output 1dB compression point
Noise figure in 50Ω
Input second-order intercept point
Input third-order intercept point
Amplifier-to-amplifier isolation
2
Saturated output power
Insertion gain when disabled
PARAMETER
TEST CONDITIONS
f = 100MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 900MHz
f = 100MHz
f = 900MHz
LIMITS
MIN
9.2
5.2
TYP
11
7.5
–14.3
–17.9
–16.5
–4.3
3.6
+4.3
–1.8
–25
–1.7
–13
–13.5
MAX
13.2
UNITS
dB
dB
dB
dB
dBm
dB
dBm
dBm
dB
dBm
dB
NOTE:
1. All measurements include the effects of the SA5200 Evaluation Board (see Figure 4). Measurement system impedance is 50Ω.
2. Input applied to one amplifier, output taken at the other output. All ports terminated into 50Ω.
1997 Nov 07
5–3
Philips Semiconductors
Product specification
RF dual gain-stage
SA5200
APPLICATIONS
SA5200 is a user-friendly, wide-band, unconditionally stable, low
power dual gain amplifier circuit. There are several advantages to
using the SA5200 as a high frequency gain block instead of a
discrete implementation. First is the simplicity of use. The SA5200
does not need any external biasing components. Due to the higher
level of integration and small footprint (SO8) package it occupies
less space on the printed circuit board and reduces the
manufacturing cost of the system. Also the higher level of
integration improves the reliability of the amplifier over a discrete
implementation with several components. The power down mode in
the SA5200 helps reduce power consumption in applications where
the amplifiers can be disabled. And last but not the least is the
impedance matching at inputs and outputs. Only those who have
toiled through discrete transistor implementations for 50Ω input and
output impedance matching can truly appreciate the elegance and
simplicity of the SA5200 input and output impedance matching to
50Ω.
A simplified equivalent schematic is shown in 3. Each amplifier is
composed of an NPN transistor with an Ft of 13GHz in a classical
series-shunt feedback configuration. The two wideband amplifiers
are biased from the same bias generator. In normal operation each
amplifier consumes about 4mA of quiescent current (at V
CC
= 5V).
In the disable mode the device consumes about 90µA of current,
most of it is in the TTL enable buffer and the bias generator. The
input impedance of the amplifiers is 50Ω. The amplifiers have
typical gain of 11dB at 100MHz and 7dB of gain at 1.2GHz.
It can be seen from 3 that any inductance between Pin 7, 3 and the
ground plane will reduce the gain of the amplifiers at higher
frequencies. Thus proper grounding of Pins 7 and 3 is essential for
maximum gain and increased frequency response. 4 shows the
printed circuit board layout and the component placement for the
SA5200 evaluation board. The AC coupling capacitors should be
selected such that at they are shorts at the desired frequency of
operation. Since most low-cost large value surface mount
capacitors cease to be simply capacitors in the UHF range and
exhibit an inductive behavior, it is recommended that high frequency
chip capacitors be utilized in the circuit. A good power supply
bypass is also essential for the performance of the amplifier and
should be as close to the device as practical.
5 shows the typical frequency response of the two channels of
SA5200. The low frequency gain is about 11dB at 100MHz and
slowly drops off to 10dB at 500MHz. The gain is about 8dB at
900MHz and 7dB at 1.2 GHz which is typical of SA5200 with a good
printed circuit board layout. It can also be seen that both channels
have a very well matched frequency response and matched gain to
within 0.1dB at 100MHz and 0.2dB at 900MHz.
SA5200 finds applications in many areas of RF communications. It
is an ideal gain block for high performance, low cost, low power RF
communications transceivers. A typical radio transceiver front-end
is shown in 6. This could be the front-end of a cellular phone, a
VHF/ UHF hand-held transceiver, UHF cordless telephone or a
spread spectrum system. The SA5200 can be used in the receiver
path of most systems as an LNA and pre-amplifier. The bandpass
filter between the two amplifiers also minimize the noise into the first
mixer. In the transmitter path, SA5200 can be used as a buffer to
the VCO and isolate the VCO from any load variations due to the
power level changes in the power amplifier. This improves the
stability of the VCOs. The SA5200 can also be used as a pre-driver
to the power amplifier modules.
The two amplifiers in SA5200 can be easily cascaded to have a
13dB gain block at 900MHz. At 100MHz the gain will be 22dB and a
noise figure of about 5.5dB. The SA5200 can be operated at a
higher voltage up to 9V for much improved 1dB output compression
point and higher 3rd order intercept point.
Several stages of SA5200 can also be cascaded and be used as an
IF amplifier strip for DBS/TV/GPS receivers. 7 shows a 60dB gain
IF strip at 180MHz. The noise figure for the cascaded amplifier
chain is given by equation 1.
NF (total) = NF1 + NF2/G1 + NF3/G1*G2 + NF4/G1*G2*G3 + ...
(Equation. 1)
NOTE: The noise figure and gain should not be in dB in the above
equation.
Since the noise figure for each stage is about 3.6dB and the gain is
about 11dB, the noise figure for the 60dB gain IF strip will be about
6.4dB.
In applications where a single amplifier is required with a 7.5dB gain
at 900MHz and current consumption is of paramount importance
(battery powered receivers), the amplifier A1 can be used and
amplifier A2 can be disabled by leaving GND2 (Pin 3) unconnected.
This will reduce the total current consumption for the IC to a meager
4mA.
The ENABLE pin is useful for Time-Division-Duplex systems where
the receiver can be disabled for a period of time. In this case the
overall system supply current will be decreased by 8mA.
The ENABLE pin can also be used to improve the system dynamic
range. For input levels that are extremely high, the SA5200 can be
disabled. In this case the input signal is attenuated by 13dB. This
prevents the system from being overloaded as well as improves the
system’s overall dynamic range. In the disabled condition the
SA5200 IP
3
increases to nearly +20dBm.
1997 Nov 07
5–4
ADI Reference Circuit
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