EEWORLDEEWORLDEEWORLD

Part Number

Search

OCD15

Description
5X7X1.6mm / SMD / HCMOS/TTL Oscillator
File Size28KB,1 Pages
ManufacturerCaliber
Websitehttp://www.caliberelectronics.com/
Download Datasheet View All

OCD15 Overview

5X7X1.6mm / SMD / HCMOS/TTL Oscillator

OC Series
5X7X1.6mm / SMD / HCMOS/TTL Oscillator
PART NUMBERING GUIDE
Package
OCH = 5X7X1.6mm / 5.0Vdc / HCMOS-TTL
OCC = 5X7X1.6mm / 5.0Vdc / HCMOS-TTL / Low Power
<25.000MHz=15mA max. / >24.000MHz=20mA max.
Lead-Free
RoHS Compliant
C A L I B E R
Electronics Inc.
Environmental/Mechanical Specifications on page F5
OCH 100 48 A T - 30.000MHz
Pin One Connection
T = Tri State Enable High
Output Symmetry
Blank = 40/60%, A = 45/55%
Operating Temperature Range
Blank = 0°C to 70°C, 27 = -20°C to 70°C, 48 = -40°C to 85°C
OCD
= 5X7X1.7mm / 5.0Vdc and 3.3Vdc / HCMOS-TTL
Inclusive Stability
100= +/-100ppm, 50= +/-50ppm, 30= +/-30ppm, 25= +/-25ppm,
20= +/-20ppm, 15= +/-15ppm, 10= ±10ppm
(25,20,15,10= 0°C-70°C Only)
ELECTRICAL SPECIFICATIONS
Frequency Range
Operating Temperature Range
Storage Temperature Range
Supply Voltage
Input Current
1.544MHz to 36.000MHz
36,001MHz to 70.000MHz
70.001MHz to 125.000MHz
Inclusive of Operating Temperature Range, Supply
Voltage and Load
w/TTL Load
w/HCMOS Load
w/TTL Load
w/HCMOS Load
Revision: 1998-C
1.544MHz to 156.520MHz
0°C to 70°C / -20°C to 70°C / -40°C to 85°C
-55°C to 125°C
5.0Vdc ±10%, 3.3Vdc ±10%
18mA Maximum
50mA Maximum
65mA Maximum
±100ppm, ±50ppm, ±30ppm, ±25ppm, ±20ppm,
±15ppm or ±10ppm
(25, 20, 15, 10 = 0°C to 70°C )
2.4Vdc Minimum
Vdd –0.5Vdc Minimum
0.4Vdc Maximum
0.5Vdc Maximum
Frequency Tolerance / Stability
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise / Fall Time
10% to 90% of Waveform w/30pF HCMOS Load; 0.4Vdc to 2.4V w/10LSTTL Load 10nSec Max. </= 70.000MHz
10% to 90% of Wavefrom w/15pF HCMOS Load; 0.4Vdc to 2.4V w/10LSTTL Load 5nSec Max. .>70.000MHz
10% to 90% of Wavefrom w/50pF HCMOS Load; 0.4Vdc to 2.4V w/TTL Load 5nSec Max. .</=70.000MHz
Duty Cycle
@1.4Vdc w/TTL Load; @50% w/HCMOS Load
@1.4Vdc w/TTL Load or w/HCMOS Load
@50% of Waveform w/LSTTL or HCMOS Load
>66.667MHz
</= 70.000MHz
>70.000MHz
</=70.000MHz (Optional)
No Connection
V
IH
V
IL
50 ±10% (Standard)
50±5% (Optional)
50±5% (Optional)
10LSTTL Load or 30pF HCMOS Load
10LSTTL Load or 15pF HCMOS Load
10TTL Load or 50pF HCMOS Load
Enables Output
+2.2Vdc Minimum to Enable Output
+0.8Vdc Maximum to Disable Output
±5ppm / year Maximum
10mSeconds Maximum
±100pSeconds Maximum
±25pSeconds Maximum
Load Drive Capability
Pin 1 Tristate Input Voltage
Aging (@ 25°C)
Start Up Time
Absolute Clock Jitter
One Sigma Clock Jitter
MECHANICAL DIMENSIONS
5.0
Max
Metal
1.0
±0.2
(X4 plcs.)
Marking Guide
1.4 ±0.2
(X4 plcs.)
All Dimensions in mm.
Line 1: Frequency
Line 2: CEI YM
4
1
5.08
±0.15
7.5
Max
3
2
T = Tristate
CEI = Caliber Electronics Inc.
YM = Date Code (Year / Month)
Ceramic
1.6
±0.2
2.20
±0.15
Pin 1: Tri-State
Pin 2: Case Ground
Pin 3: Output
Pin 4: Supply Voltage
TEL
949-366-8700
FAX
949-366-8707
WEB
http://www.caliberelectronics.com
About IS61lv25616
read timingwrite timing How to understand this timing...
phdwong FPGA/CPLD
LM3S8962 Evaluation Kit User Report
On Wednesday, the teacher taught us how to use the LM3S8962 evaluation kit. The teacher used the kit to demonstrate a steam locomotive. The black and white pictures were displayed on the small screen....
sjhjz Microcontroller MCU
Topic: Comprehensive Analysis of Analog Devices Blackfin Processor
Topic: Comprehensive Analysis of Analog Devices Blackfin Processor...
maker MCU
Building a BLE development environment
[i=s]This post was last edited by alan000345 on 2019-2-27 09:55[/i] [align=left][color=rgb(85, 85, 85)][font="][size=14px]1.1 Hardware Preparation[/size][/font][/color][/align][align=left][color=rgb(8...
alan000345 Wireless Connectivity
I have money now. I received a 7-piece travel package from VISHAY today.
I will have money soon. Today I received a prize from VISHAY, a 7-piece travel set. I saw the post the day before yesterday. Thank you VISHAY, thank you eeworld, I will have money soon....
maoshen Talking
Xilinx Design contest
Xilinx Design contest is about Xilinx's first innovative design contest. Main content: Design of JPEG hardware decoder based on FPGA....
liwenqi FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2586  1288  1822  2048  852  53  26  37  42  18 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号