BU-64845G4-530 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> BU-64845G4-530

BU-64845G4-530: DescriptionSerial IO/Communication Controller, CMOS, CQFP80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，95 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

BU-64845G4-530 Overview

Serial IO/Communication Controller, CMOS, CQFP80

BU-64845G4-530 Parametric

Parameter Name	Attribute value
Objectid	1154990265
Parts packaging code	QFP
package instruction	QFP, QFP80,1.1SQ,40
Contacts	80
Reach Compliance Code	compliant
Other features	SEATED HGT-CALCULATED, ALSO SUPPORTS MIL-STD-1553A
Address bus width	16
boundary scan	NO
maximum clock frequency	20 MHz
letter of agreement	MIL-STD-1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	S-CQFP-G80
length	22.35 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	80
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP
Encapsulate equivalent code	QFP80,1.1SQ,40
Package shape	SQUARE
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
Filter level	MIL-PRF-38534
Maximum seat height	3.708 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.016 mm
Terminal location	QUAD
width	22.35 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553

Preview

Download Datasheet

View All

Make sure the next

Card you purchase

has...

BU-6474X/6484X/6486X

MINI-ACE

MARK3/MICRO-ACE

*-TE

FEATURES

•

Fully Integrated 3.3 or 5.0 Volt, 1553

A/B Notice 2 Terminal

•

World’s First all 3.3 Volt Terminal

•

Transceiver Power-Down Options

•

World’s Smallest CQFP MIL-STD-1553

Device

•

80-pin Ceramic Flat/Gull Wing

Package or 324-Ball BGA Package

•

Enhanced Mini-ACE Architecture

•

Multiple Configurations:

- RT-only, 4K RAM

- BC/RT/Monitor, 4K RAM

DESCRIPTION

The Mini-ACE Mark3 and Micro-ACE-TE are the world's first MIL-STD-1553

terminals which can be powered entirely by +3.3 volts, thus eliminating the

need for a +5 volt power supply. With a package body of 0.880 inches square

and a gull wing "toe-to-toe" dimension of 1.110 inches, the Mini-ACE Mark3

is the industry's smallest ceramic gull-lead 1553 terminal. At 0.815 inches

square, the Micro-ACE-TE (BGA package) provides the smallest industry

footprint, enabling its use in applications where PC board space is at a pre-

mium.

These devices integrate dual 3.3 or 5 volt transceivers, 3.3 or 5.0 volt protocol

logic, and either 4K or 64K words of internal RAM. The architecture is identi-

cal to that of the Enhanced Mini-ACE, and most features are functionally and

software compatible with the previous Mini-ACE (Plus) and ACE genera-

tions.

A salient feature of the Mini-ACE Mark3 and Micro-ACE-TE is the advanced

bus controller architecture. This provides methods to control message sched-

uling, the means to minimize host overhead for asynchronous message

insertion, facilitate bulk data transfers and double buffering, and support

various message retry and bus switching strategies.

The remote terminal architecture provides flexibility in meeting all common

MIL-STD-1553 protocols. The choice of RT data buffering and interrupt

options provides robust support for synchronous and asynchronous messag-

ing, while ensuring data sample consistency and supporting bulk data trans-

fers. The monitor mode provides true message monitoring, and supports fil-

tering on an RT address/T-R bit/subaddress basis.

The Mini-ACE Mark3 and Micro-ACE-TE incorporate fully autonomous built-

in self-tests of internal protocol logic and RAM. The terminals provide

the

same flexibility in host interface configurations as the ACE/Mini-ACE, along

with a reduction in the host processor's worst case holdoff time.

- BC/RT/Monitor, 64K RAM

•

Supports 1553A/B Notice 2, McAir,

STANAG 3838 Protocols

•

MIL-STD-1553, McAir, and MIL-

STD-1760 Transceiver Options

•

Highly Flexible Host Side Interface

•

Compatible With Mini-ACE and ACE

Generations

•

Highly Autonomous BC with Built-In

Message Sequence Controller

•

Choice of Single, Double, and

Circular RT Buffering Options

•

Selective Message Monitor

•

Comprehensive Built-In Self-Test

•

Choice Of 10, 12, 16, or 20 MHz Clock

Inputs

•

Software Libraries and Drivers

available for Windows® 9x/2000/XP,

Windows NT®, VxWorks® and Linux

•

Available with Full Military

Temperature Range and Screening

FOR MORE INFORMATION CONTACT:

Technical Support:

1-800-DDC-5757 ext. 7771

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

subject to one or more patents pending.

All trademarks are the property of their respective owners.

The technology used in DDC’s Micro-ACE series of products may be

Recommended Resources

Anti-theft alarm circuit 2 with warning wires

Constant current parallel voltage stabilized power supply circuit diagram composed of LM317

Sample and hold circuit diagram

Active high power factor correction pre-regulator circuit diagram using UC3852

FM walkie-talkie circuit

Four-phase clock source

PCBеEMC: [color=red][b]Please log in before downloading[/b][/color]...; 护花使者 FPGA/CPLD

How to use bdata?: uchar bdata LedState = 0xFF;sbit LedAh = LedState^0;sbit LedAl = LedState^1; sbit LedK = LedState^2;sbit LedM = LedState^3;uchar bdata KeySign; sbit FirstPress = KeySign^4; sbit AffirmPress = KeySign^...; 1614048761 MCU

Introduction to Power Factor Correction Technology in AC/DC Front-End Converter Modules: [i=s] This post was last edited by fish001 on 2019-5-20 22:28 [/i] [p=30, 2, left][size=4] By definition, the power factor (PF) of an AC power supply is defined as the ratio of the real power (watts) ...; fish001 Analogue and Mixed Signal

Does vxworks support hyperthreading/multithreaded cpu? What components are needed? Is there any difference between the upper layer software and single threaded cpu?: Does vxworks support hyperthreading/multithreaded cpu? What components are needed? Is there any difference between the upper layer software and single threaded cpu?...; fpgafuns Real-time operating system RTOS

How to see which registers are synthesized in Quartus II9.0, privileged brother Johnson: During the experiment, did you pay attention to the rtl code? I wrote the program according to his video, but some registers were missing. The methods on the Internet didn't work, and I didn't see it ...; prayer_hong FPGA/CPLD

The problem of porting DSP algorithms from PC.: I need to port an image processing program from PC to DSP . The DSP model is DM642. After modifying the C++ program on PC to compile under DSP , it still has problems when running. The ported program ...; 821165254 DSP and ARM Processors

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components