1 CHIP CODEC
S5T8554B/7B
INTRODUCTION
16-CERDIP
The S5T8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide all the
functions required to interface a full-duplex voice telephone circuit
with a time-division-multiplex (TDM) system.
These devices are designed to perform the transmit encoding and
receive decoding as well as the transmit and receive filtering
functions in PCM system. They are intended to be used at the
analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog signals
prior to encoding and after decoding. These combination devices
perform the encoding and decoding of voice and call progress tones
as well as the signalling and supervision information.
16-DIP-300A
8−DIP−300
FEATURES
•
•
•
•
•
•
•
Complete CODEC and filtering system
Meets or exceeds AT&T D3/D4 and CCITT specifications
µ-Law:
S5T8554B, A-Law: S5T8557B
On-chip auto zero, sample and hold, and precision voltage references
Low power dissipation: 60mW (operating), 3mW (standby)
± 5V operation
TTL or CMOS compatible
Automatic power down
ORDERING INFORMATION
Device
S5T8554B02-L0B0
S5T8557B02-L0B0
S5T8554B01-D0B0
S5T8557B01-D0B0
S5T8554B01-S0B0
S5T8557B01-S0B0
Package
16-CERDIP
16-DIP-300A
16-SOP-BD300
Operating Temperature
−25°C
to 125°C
−25°C
to +70°C
−25°C
to +70°C
1
S5T8554B/7B
1 CHIP CODEC
PIN CONFIGURATION
V
BB
GNDA
VF
R
O
V
CC
FS
R
D
R
BCLK
R
/CLKSEL
MCLK
R
/PDN
1
2
3
4
5
6
7
8
16 VF
X
I
+
15 VF
X
I
-
14 GS
X
13 TS
X
12 FS
X
S
11 D
X
10 BCLK
X
9
MCLK
X
S5T8554B/7B
KT8554/7
PIN DISCRIPTION
Pin No
1
2
3
4
5
6
7
Symbol
V
BB
GNDA
VF
R
O
V
CC
FS
R
D
R
BLCK
R
/
CLKSEL
MCLK
R
/
PDN
MCLK
X
BLCK
X
D
X
FS
X
TS
X
GS
X
VF
X
I
−
VF
X
I
+
V
BB
=
−5V ±
5%
Analog ground.
Analog output of the receive power Amp.
V
CC
= +5 V
±
5%
Receive frame sync pulse. 8kHz pulse train
PCM data input.
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock
in normal operation and BCLK
X
is used for both TX and RX directions.
Alternately direct clock input available, vary from 60kHz to 2.048MHz.
When MCLK
R
is connected continuously high, the device is powered down.
Normally connected continuously low, MCLK
X
is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.
Must be 1.536MHz/1.544MHz or 2.048MHz.
May be vary from 64kHz to 2.048MHz but BCLK
X
is externally tied with MCLK
X
in
normal operation.
PCM data output.
TX frame sync pulse. 8kHz pulse train.
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier. Used to set gain through external resistor.
Inverting input stage of the TX analog signal.
Non-inverting input stage of the TX analog signal.
Description
8
9
10
11
12
13
14
15
16
2
1 CHIP CODEC
S5T8554B/7B
ABSOLUTE MAXIMUM RATING
Characteristic
Positive Supply Voltage
Negative Supply Voltage
Voltage at Any Analog Input or Output
Voltage at Any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 secs)
Symbol
V
CC
V
BB
V
I (A)
V
I (D)
Ta
T
STG
T
LEAD
Value
7
−7
V
CC
+ 0.3 ~ V
BB
- 0.3
V
CC
+ 0.3 ~ GND
A
- 0.3
−25
~ +125
−65
~ +150
300
Unit
V
V
V
V
°C
°C
°C
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
±
5%, V
BB
=
−5.0V ±
5%, GND
A
= 0V, Ta = 0°C to 70°C;
typical characteristics specified at V
CC
= 5.0V, V
BB
=
−5.0V,
Ta=25°C; all signals referenced to GND
A
)
Characteristic
POWER DISSIPATION
Power-Down Current
Power-Down Current
Active Current
Active Current
DIGITAL INTERFACE
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
V
IL
V
IH
I
IL
I
IH
V
OL
−
−
GND
A
≤
V
IN
≤
V
IL
, all digital input
V
IH
≤
V
IN
≤
V
CC
D
X
, I
L
= 3.2mA
SIG
R
, I
L
= 1.0mA
TS
X
, I
L
= 3.2mA, open drain
D
X
, I
H
=
−3.2mA
SIG
R
, I
H
=
−1.0mA
D
X
, GND
A
≤
V
O
≤
V
CC
−
2.2
−10
−10
−
−
−
−
−
−
0.6
−
10
10
0.4
0.4
0.4
−
10
V
V
µA
µA
V
V
V
V
V
µA
I
CC (DOWN)
No Load
I
BB (DOWN)
No Load
I
CC (A)
I
BB (A)
No Load
No Load
−
−
−
−
0.5
0.05
6.0
6.0
1.5
0.3
9.0
9.0
mA
mA
mA
mA
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Output High Voltage
Output Current in High
Impedance State (Tri -state)
I
O (HZ)
I
O (HZ)
2.4
2.4
−10
−
−
ANALOG INTERFACE WITH RECEIVE FILTER
Output Resistance
R
O
Pin VF
R
O
−
1
3
Ω
3
S5T8554B/7B
1 CHIP CODEC
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
±
5%, V
BB
=
−5.0V ±
5%, GND
A
= 0V, Ta = 0°C to 70°C;
typical characteristics specified at V
CC
= 5.0V, V
BB
=
−5.0V,
Ta=25°C; all signals referenced to GND
A
)
Characteristic
Load Resistance
Load Capacitance
Output DC Offset Voltage
Symbol
R
L
C
L
V
OO (RX)
Test Conditions
VF
R
O = ± 2.5V
−
−
Min.
600
−
−200
−200
10
−
10
−
±
2.8
5,000
−
−
CMRRXA > 60dB
DC Test
DC Test
1
−20
−2.5
60
60
Typ.
−
−
−
−
−
1
−
−
−
−
2
−
−
−
−
Max.
−
500
200
Unit
Ω
pF
mV
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER
Input Leakage Current
Input Resistance
Output Resistance
Load Resistance
Load Capacitance
Output Dynamic Range
Voltage Gain
Unity Gain Bandwidth
Offset Voltage
Common-Mode Voltage
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
I
LKG
R
I
R
O
R
L
C
L
V
OD (TX)
G
V
BW
V
IO (TX)
V
CM (TX)
CMRR
PSRR
-2.5V≤V≤+2.5V, VF
X
I+ or VF
X
I-
-2.5V≤V≤+2.5V, VF
X
I+ or VF
X
I-
Closed loop, unity gain
GS
X
GS
X
GS
X
, R
L
≤10KW
VF
X
I+ to GSX
200
−
3
−
50
−
−
−
20
2.5
−
−
nA
MΩ
Ω
kΩ
pF
V
V/N
MHz
mV
V
dB
dB
4
1 CHIP CODEC
S5T8554B/7B
TIMING CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
±
5%, V
BB
=
−5.0V ±
5%, GND
A
= 0V, Ta = 0°C to 70°C;
typical characteristics specified at V
CC
= 5.0V, V
BB
=
−5.0V,
Ta=25°C; all signals referenced to GND
A
)
Characteristic
Frequency of Master Clock
Symbol
f
MCK
Test Conditions
Depends on the device used
and the BCLK
R
/CLKSEL Pin.
MCLK
X
and MCLK
R
t
PB
= 488ns
t
PB
= 488ns
Long frame only
Short frame only
Long frame only
Load = 150pF plse 2 LSTTL
loads
Load = 150pF plse 2 LSTTL
loads
−
C
L
= 0pF to 150pF
Min.
−
Typ.
1.536
1.544
2.048
−
−
−
−
−
−
−
−
−
Max.
−
Unit
nS
Rise Time of Bit Clock
Fall Time of Bit Clock
Holding Time from Bit Clock
Low to Frame Sync
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
Delay Time from BCLK
X
High
to Data Valid
Delay Time to TS
X
Low
Delay Time from BCLK
X
Low to
Data Output Disabled
Delay Time to Valid Data from
FSX or BCLK
X
, Whichever
Comes Later
Set-Up Time from D
R
Valid to
BCLK
R/X
Low
Hold Time from FS
R/X
Low to
D
R
Invalid
Set-Up Time from FS
R/X
to
BCLK
R/X
Low
Width of Master Clock High
Width of Master Clock Low
Rise Time of Master Clock
Fall Time of Master Clock
Set-Up Time from BCLK
X
High
(and FS
X
In Long Frame Sync
Mode) to MCLK
X
Falling Edge
t
R (BCK)
t
F (BCK)
t
H (LFS)
t
H (RFS)
t
SU (FBCL)
t
D (HDV)
t
D (TSXL)
t
D (LDD)
t
D (VD)
−
−
0
0
80
0
−
50
20
50
50
−
−
−
180
140
165
165
nS
nS
nS
nS
nS
nS
nS
nS
nS
t
SU (DRBL)
t
H (BLDR)
t
SU (FBLS)
t
W (MCKH)
t
W (MCKL)
t
R (MCK)
t
F (MCK)
t
SU (BHMF)
−
−
Short frame sync pulse (1 or 2
bit clock periods long) (Note 1)
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
First bit clock after the leading
edge FS
X
50
50
50
160
160
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
50
50
−
nS
nS
nS
nS
nS
nS
nS
−
5
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