128Mb: x4, x8, x16
SDRAM 3.3V
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
:
Vdd = 3.3V
±
10%V, Temp.
=
25° to 70
°C
Supply Current
OPERATING CURRENT:
ACTIVE mode, burst = 1, READ or WRITE, tRC > tRC
(MIN), one bank active, CL=3
STANDBY CURRENT:
POWER-DOWN mode, CKE = LOW,
Standard parts
no accesses in progress
Self refresh parts
STANDBY CURRENT:
CS# = HIGH, CKE = HIGH, all banks idle
STANDBY CURRENT:
CS# = HIGH, CKE = HIGH, all banks active after tRCD met,
no accesses in progress.
OPERATING CURRENT:
BURST mode after tRCD met, continuous burst, READ,
WRITE, all banks active, CL=3
AUTO REFRESH CURRENT
tRC > tRC (MIN)
CL = 3
AUTO REFRESH CURRENT
tRC=15.6us
CL = 3
SELF REFRESH CURRENT
(Self refresh parts only, part M)
Symbol
Icc1
Idd2
Idd2
Icc3
Icc4
Icc5
Icc6
Icc7
Idd8
-75A
165
9
3
75
75
165
265
50
3
-8A
140
9
3
60
50
145
245
50
3
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1, 2, 3, 4
32
32
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
Notes
1. All voltages referenced to Vss.
2. An initial pause of 100
µs
is required after power-up, followed by two AUTO REFRESH commands, before proper device operation
is ensure. (Vdd and VddQ must be powered-up simultaneously Vss and VssQ must be at the same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the
t
REF refresh requirement is exceeded.
3. Icc specifications are tested after the device is properly initialized. tCK= 10ns for –8 and tCK=7.5ns for –75A.
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
3
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice.
©
2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16
SDRAM 3.3V
AC ELECTRICAL CHARACTERISTICS:
Vdd = 3.3V
±
10%V, Temp. = 25° to 70°C
AC CHARACTERISTICS
PARAMETER
Access time from CLK (positive edge) CL = 3
Access time from CLK (positive edge) CL = 2
Address hold time
Address setup time
CLK high level width
CLK low level width
Clock cycle time CL = 3
Clock cycle time CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high impedance time
Data-out low impedance time
Data-out hold time
ACTIVE to PRECHARGE command period
AUTO REFRESH to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4096 cycles)
PRECHARGE command period
ACTIVE bank A to bank B command period
Transition time
Write recovery time
Exit SELF REFRESH to ACTIVE command
READ/WRITE command to READ/WRITE command
CKE to clock disable or power down entry mode
CKE to clock enable or power down exit setup
SYMBOL
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tLZ
tOH
tRAS
tRC
tRCD
tREF
tRP
tRRD
tT
tWR
tXSR
tCCD
tCKED
tPED
-75A
MIN
-75A
MAX
5.4
N/A
-8A
MIN
-8A
MAX
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
tCK
tCK
tCK
tCK
NOTES
0.8
1.5
2.5
2.5
7.5
N/A
0.8
1.5
0.8
1.5
0.8
1.5
9
1
2.7
44
60
22.5
22.5
15
0.3
20
8
1
1
1
1
2
3
3
10
1
2
1
2
1
2
9
2
3
50
80
30
30
20
0.3
20
8
1
1
1
4
16K
16K
64
64
2
2
3
1
2
2
AC ELECTRICAL CHARACTERISTICS:
Vdd = 3.3V
±
10%V, Temp. = 25° to 70°C
AC CHARACTERISTICS
PARAMETER
DQM to input data delay
WRITE command to input data delay
Data-in to ACTIVATE command w/ Auto precharge
Data-in to precharge
Last data-in to precharge command
LOAD MODE REGISTER command to command
Data-out to high impedance from precharge
SYMBOL
tDQD
tDWD
tDAL
tDPL
tRDL
tMRD
tROH
-75A
MIN
0
0
5
2
2
2
3
-75A
MAX
-8
MIN
0
0
5
2
2
2
3
-8
MAX
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
1
1
3
2, 3
1
1
1
NOTES:
1. Clocks required specified by JEDEC functionality and not dependent on any timing parameter.
2. Timing actually specified by tCKS, clock(s) specified as a reference only at a minimum cycle rate.
3. Timing actually specified by tWR plus tRP clock(s) specified as a reference only at a minimum cycle rate.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. The last valid data
element will meet tOH before going high-Z.
5. Based on tCK = 10ns for –8 and tCK = 7.5ns for –75a
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
4
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice.
©
2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16
SDRAM 3.3V
54-PIN PLASTIC TSOP (400 mil)
(Package TK)
NOTE:
1. All dimensions in millimeters MAX/MIN or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
5
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice.
©
2001, 2002, 2004 SpecTek
Embedded System
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