ML12202
MECL PLL Components Serial
Input PLL Frequency Synthesizer
Legacy Device:
Motorola MC12202
The ML12202 is a 1.1 GHz Bipolar monolithic serial input
phase locked loop (PLL) synthesizer with pulse–swallow func-
tion. It is designed to provide the high frequency local oscillator
signal of an RF transceiver in handheld communication applica-
tions.
The technology is utilized allows for low power operation at a
minimum supply voltage of 2.7 V. The device is designed for
operation over 2.7 to 5.5 V supply range for input frequencies up
to 1.1 GHz with a typical current drain of 6.5 mA. The low
power consumption makes the ML12202 ideal for handheld bat-
tery operated applications such as cellular or cordless tele-
phones, wireless LAN or personal communication services. A
dual modulus prescaler is integrated to provide either a 64/65 or
128/129 divide ratio.
• Low Power Supply Current of 5.8 mA Typical for ICC and
0.7 mA Typical for IP
• Supply Voltage of 2.7 to 5.5 V
• Dual Modulus Prescaler With Selectable Divide Ratios of
64/65 or128/129
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a Binary
14–Bit Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit
Swallow Counter and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First Stage of
the Loop Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of TA = –40 to 85°C
NOTE:
Also available is the ML12210, a 2.5 GHz version of
this function.
Note:
Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from
ML
to
MLE.
Page 1 of 11
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Issue A
ML12202
LANSDALE Semiconductor, Inc.
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit pro-
grammable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts
one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into
the latch when load enable pin is HIGH or OPEN.
Control bit:
“H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which
will affect the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If
the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8
to 16383) and the prescaler divide ratio (SW = 0 for ÷128/129, SW = 1 for ÷64/65). An R divide ratio less than 8 is prohibited.
Page 4 of 11
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Issue A
FPGA/CPLD
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