Intel® 3000 and 3010 Chipset
Memory Controller Hub (MCH)
Datasheet
November 2008
Reference Number: 313953 Revision: 002
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Copyright© 2006, Intel Corporation
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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Contents
1
Introduction............................................................................................................... 13
1.1
Terminology ..................................................................................................... 15
1.2
Reference Documents ........................................................................................ 16
1.3
MCH Overview .................................................................................................. 17
1.3.1 Host Interface........................................................................................ 17
1.3.2 System Memory Interface ....................................................................... 17
1.3.3 Direct Media Interface (DMI).................................................................... 18
1.3.4 PCI Express* Interface(s)........................................................................ 18
1.3.5 System Interrupts .................................................................................. 19
1.3.6 MCH Clocking ........................................................................................ 19
1.3.7 Power Management ................................................................................ 20
Signal Description....................................................................................................... 21
2.1
Host Interface Signals ........................................................................................ 23
2.2
DDR2 DRAM Channel A Interface ......................................................................... 25
2.3
DDR2 DRAM Channel B Interface ......................................................................... 26
2.4
DDR2 DRAM Reference and Compensation ............................................................ 27
2.5
PCI Express* Interface Signals ............................................................................ 27
2.6
Clocks, Reset, and Miscellaneous ......................................................................... 28
2.7
Direct Media Interface (DMI)............................................................................... 28
2.8
Power, Ground .................................................................................................. 29
2.9
Reset States and Pull-up/Pull-downs .................................................................... 29
MCH Register Description ............................................................................................ 33
3.1
Register Terminology ......................................................................................... 34
3.2
Platform Configuration ....................................................................................... 35
3.3
Configuration Mechanism ................................................................................... 37
3.3.1 Standard PCI Configuration Mechanism ..................................................... 37
3.3.2 PCI Express Enhanced Configuration Mechanism......................................... 38
3.4
Routing Configuration Accesses ........................................................................... 39
3.4.1 Internal Device Configuration Accesses ..................................................... 41
3.4.2 Bridge Related Configuration Accesses ...................................................... 41
3.5
I/O Mapped Registers ........................................................................................ 42
3.5.1 CONFIG_ADDRESS—Configuration Address Register ................................... 43
3.5.2 CONFIG_DATA—Configuration Data Register .............................................. 44
Host Bridge Registers (Device 0, Function 0) .................................................................. 45
4.1
Configuration Register Details (D0:F0) ................................................................. 47
4.1.1 VID—Vendor Identification (D0:F0)........................................................... 47
4.1.2 DID—Device Identification (D0:F0) ........................................................... 47
4.1.3 PCICMD—PCI Command (D0:F0) .............................................................. 48
4.1.4 PCISTS—PCI Status (D0:F0) .................................................................... 49
4.1.5 RID—Revision Identification (D0:F0) ......................................................... 50
4.1.6 CC—Class Code (D0:F0) .......................................................................... 50
4.1.7 MLT—Master Latency Timer (D0:F0) ......................................................... 50
4.1.8 HDR—Header Type (D0:F0) ..................................................................... 51
4.1.9 SVID—Subsystem Vendor Identification (D0:F0)......................................... 51
4.1.10 SID—Subsystem Identification (D0:F0) ..................................................... 51
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ....................................................... 52
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ................................................ 52
4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address (D0:F0) ......... 53
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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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4.2
4.3
4.1.14 PCIEXBAR—PCI Express Register Range Base Address (D0:F0) .....................53
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) .....................55
4.1.16 DEVEN—Device Enable (D0:F0) ................................................................56
4.1.17 DEAP - DRAM Error Address Pointer (D0:F0)...............................................56
4.1.18 DERRSYN - DRAM Error Syndrome (D0:F0) ................................................57
4.1.19 DERRDST - DRAM Error Destination (D0:F0)...............................................57
4.1.20 PAM0—Programmable Attribute Map 0 (D0:F0) ...........................................58
4.1.21 PAM1—Programmable Attribute Map 1 (D0:F0) ...........................................59
4.1.22 PAM2—Programmable Attribute Map 2 (D0:F0) ...........................................59
4.1.23 PAM3—Programmable Attribute Map 3 (D0:F0) ...........................................60
4.1.24 PAM4—Programmable Attribute Map 4 (D0:F0) ...........................................60
4.1.25 PAM5—Programmable Attribute Map 5 (D0:F0) ...........................................61
4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0) ...........................................61
4.1.27 LAC—Legacy Access Control (D0:F0) .........................................................62
4.1.28 REMAPBASE - Remap Base Address Register ..............................................63
4.1.29 REMAPLIMIT - Remap Limit Address Register..............................................63
4.1.30 TOLUD—Top of Low Usable DRAM (D0:F0) .................................................64
4.1.31 SMRAM—System Management RAM Control (D0:F0)....................................64
4.1.32 ESMRAMC—Extended System Management RAM Control (D0:F0) ..................65
4.1.33 TOM - Top of Memory..............................................................................66
4.1.34 ERRSTS—Error Status (D0:F0) .................................................................67
4.1.35 ERRCMD—Error Command (D0:F0) ...........................................................68
4.1.36 SMICMD - SMI Command (D0:F0).............................................................69
4.1.37 SCICMD - SCI Command (D0:F0) .............................................................69
4.1.38 SKPD—Scratchpad Data (D0:F0)...............................................................70
4.1.39 CAPID0—Capability Identifier (D0:F0) .......................................................70
4.1.40 EDEAP—Extended DRAM Error Address Pointer (D0:F0) ...............................70
MCHBAR Configuration Register Details.................................................................71
4.2.1 C0DRB0—Channel A DRAM Rank Boundary Address 0..................................72
4.2.2 C0DRB1—Channel A DRAM Rank Boundary Address 1..................................73
4.2.3 C0DRB2—Channel A DRAM Rank Boundary Address 2..................................73
4.2.4 C0DRB3—Channel A DRAM Rank Boundary Address 3..................................73
4.2.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute ............................................74
4.2.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute ............................................74
4.2.7 C0DCLKDIS—Channel A DRAM Clock Disable ..............................................75
4.2.8 C0BNKARC—Channel A DRAM Bank Architecture .........................................76
4.2.9 C0DRT1—Channel A DRAM Timing Register ...............................................76
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 .............................................77
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 .............................................78
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0..................................79
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1..................................79
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2..................................79
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3..................................79
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................................79
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................................79
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ..............................................80
4.2.19 C1BNKARC—Channel B Bank Architecture ..................................................80
4.2.20 C1DRT1—Channel 1 DRAM Timing Register 1 .............................................80
4.2.21 C1DRC0—Channel 1 DRAM Controller Mode 0 .............................................80
4.2.22 C1DRC1—Channel 1 DRAM Controller Mode 1 .............................................80
4.2.23 PMCFG—Power Management Configuration.................................................81
4.2.24 PMSTS—Power Management Status...........................................................81
Egress Port Register Summary ............................................................................82
4.3.1 EPESD—EP Element Self Description..........................................................83
4.3.2 EPLE1D—EP Link Entry 1 Description .........................................................83
4.3.3 EPLE1A—EP Link Entry 1 Address..............................................................84
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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
4.3.4
4.3.5
4.3.6
4.3.7
5
EPLE2D—EP Link Entry 2 Description......................................................... 84
EPLE2A—EP Link Entry 2 Address ............................................................. 85
EPLE3D-EP Link Entry 3 Description .......................................................... 85
EPLE3A—EP Link Entry 3 Address ............................................................. 86
Host-PCI Express Bridge Registers (D1:F0) .................................................................... 87
5.1
Configuration Register Details (D1:F0) ................................................................. 90
5.1.1 VID1—Vendor Identification (D1:F0) ......................................................... 90
5.1.2 DID1—Device Identification (D1:F0) ......................................................... 90
5.1.3 PCICMD1—PCI Command (D1:F0) ............................................................ 90
5.1.4 PCISTS1—PCI Status (D1:F0) .................................................................. 92
5.1.5 RID1—Revision Identification (D1:F0) ....................................................... 93
5.1.6 CC1—Class Code (D1:F0) ........................................................................ 93
5.1.7 CL1—Cache Line Size (D1:F0) .................................................................. 93
5.1.8 HDR1—Header Type (D1:F0) ................................................................... 94
5.1.9 PBUSN1—Primary Bus Number (D1:F0)..................................................... 94
5.1.10 SBUSN1—Secondary Bus Number (D1:F0)................................................. 94
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ............................................ 95
5.1.12 IOBASE1—I/O Base Address (D1:F0) ........................................................ 95
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ....................................................... 95
5.1.14 SSTS1—Secondary Status (D1:F0) ........................................................... 96
5.1.15 MBASE1—Memory Base Address (D1:F0)................................................... 97
5.1.16 MLIMIT1—Memory Limit Address (D1:F0) .................................................. 97
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ............................... 98
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) .............................. 98
5.1.19 PMBASEU1—Prefetchable Memory Base Address ......................................... 99
5.1.20 PMLIMITU1—Prefetchable Memory Limit Address ........................................ 99
5.1.21 CAPPTR1—Capabilities Pointer (D1:F0) .................................................... 100
5.1.22 INTRLINE1—Interrupt Line (D1:F0)......................................................... 100
5.1.23 INTRPIN1—Interrupt Pin (D1:F0)............................................................ 101
5.1.24 BCTRL1—Bridge Control (D1:F0) ............................................................ 101
5.1.25 PM_CAPID1—Power Management Capabilities (D1:F0)............................... 102
5.1.26 PM_CS1—Power Management Control/Status (D1:F0) ............................... 103
5.1.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ................... 104
5.1.28 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) .............................. 104
5.1.29 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0)................. 104
5.1.30 MC—Message Control (D1:F0)................................................................ 105
5.1.31 MA—Message Address (D1:F0)............................................................... 106
5.1.32 MD—Message Data (D1:F0) ................................................................... 106
5.1.33 PCI_EXPRESS_CAPL—PCI Express Link Capability List (D1:F0) ................... 106
5.1.34 PCI_EXPRESS_CAP—PCI Express Link Capabilities (D1:F0) ........................ 107
5.1.35 DCAP—Device Capabilities (D1:F0) ......................................................... 107
5.1.36 DCTL—Device Control (D1:F0) ............................................................... 108
5.1.37 DSTS—Device Status (D1:F0) ................................................................ 108
5.1.38 LCAP—Link Capabilities (D1:F0) ............................................................. 109
5.1.39 LCTL—Link Control (D1:F0) ................................................................... 110
5.1.40 LSTS—Link Status (D1:F0) .................................................................... 111
5.1.41 SLOTCAP—Slot Capabilities (D1:F0) ........................................................ 112
5.1.42 SLOTCTL—Slot Control (D1:F0) .............................................................. 113
5.1.43 SLOTSTS—Slot Status (D1:F0) ............................................................... 114
5.1.44 RCTL—Root Control (D1:F0) .................................................................. 114
5.1.45 RSTS—Root Status (D1:F0) ................................................................... 115
5.1.46 PCI_EXPRESS_LC—PCI Express link Legacy Control .................................. 116
5.1.47 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) .................... 116
5.1.48 PVCCAP1—Port VC Capability Register 1 (D1:F0) ...................................... 117
5.1.49 PVCCAP2—Port VC Capability Register 2 (D1:F0) ...................................... 117
5.1.50 PVCCTL—Port VC Control (D1:F0) ........................................................... 118
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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