SSM6J503NU
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM6J503NU
Power Management Switch Applications
•
•
1.5V drive
Low ON-resistance: R
DS(ON)
= 89.6 mΩ (max) (@V
GS
= -1.5 V)
R
DS(ON)
= 57.9 mΩ (max) (@V
GS
= -1.8 V)
R
DS(ON)
= 41.7 mΩ (max) (@V
GS
= -2.5 V)
R
DS(ON)
= 32.4 mΩ (max) (@V
GS
= -4.5 V)
Unit: mm
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristics
Drain-Source voltage
Gate-Source voltage
Drain current
DC
Pulse
Symbol
V
DSS
V
GSS
I
D
I
DP
(Note 1)
P
D
(Note 2)
t
≦10s
T
ch
T
stg
Rating
−20
±8
−6.0
-24.0
1
2
150
−55
to 150
Unit
V
V
A
Power Dissipation
Channel temperature
Storage temperature
W
°C
°C
Note:
UDFN6B
Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
JEDEC
―
temperature, etc.) may cause this product to decrease in the
JEITA
―
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
TOSHIBA
2-2AA1A
absolute maximum ratings.
Weight: 8.5 mg (typ.)
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and
estimated failure rate, etc).
1,2,5,6: Drain
3: Gate
4: Source
Note 1: The pulse width limited by max channel temperature.
Note 2: Mounted on an FR4 board.
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
Marking(Top View)
6
5
4
Equivalent Circuit(Top View)
6
5
4
Pin Condition(Top View)
6
5
4
SP3
Drain
1
1
2
3
2
3
Source
1
2
3
Polarity marking
Polarity marking (on the top)
*Electrodes : on the bottom
Start of commercial production
2010-11
1
2014-03-01
SSM6J503NU
Electrical Characteristics
(Ta
=
25°C)
Characteristic
Drain-Source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Symbol
V
(BR) DSS
V
(BR) DSX
I
DSS
I
GSS
V
th
|Y
fs
|
Test Conditions
I
D
=
-1 mA, V
GS
=
0 V
I
D
=
-1 mA, V
GS
=
5 V
V
DS
=
-20 V, V
GS
=
0 V
V
GS
= ±8
V, V
DS
=
0 V
V
DS
=
-3 V, I
D
=
-1 mA
V
DS
=
-3 V, I
D
=
-1.0 A
I
D
=
-3.0 A, V
GS
=
-4.5 V
Drain–source ON-resistance
R
DS (ON)
I
D
=
-2.5 A, V
GS
=
-2.5 V
I
D
=
-1.5 A, V
GS
=
-1.8 V
I
D
=
-0.5 A, V
GS
=
-1.5 V
Input capacitance
Output capacitance
Reverse transfer capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Switching time
Turn-on time
Turn-off time
C
iss
C
oss
C
rss
Q
g
Q
gs1
Q
gd
t
on
t
off
V
DSF
V
DD
=
−10
V, I
D
=
−4.0
A
V
GS
=
−4.5
V
V
DD
=
-10 V, I
D
=
-2.0 A,
V
GS
=
0 to -2.5 V, R
G
=
4.7
Ω
I
D
=
4.0 A, V
GS
=
0 V
(Note 3)
V
DS
=
-10 V, V
GS
=
0 V, f
=
1 MHz
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 4)
Min
-20
-15
―
―
-0.3
4.5
―
―
―
―
―
―
―
―
―
―
―
―
―
Typ.
―
―
―
―
―
9.1
27.7
33.1
40.6
48.6
840
118
99
12.8
1.4
3.0
32
107
0.78
Max
―
―
-1
±1
-1.0
―
32.4
41.7
57.9
89.6
―
―
―
―
―
―
―
―
1.2
ns
V
nC
pF
mΩ
Unit
V
μA
μA
V
S
Drain-Source forward voltage
Note 3: Pulse test
Note 4: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode.
Note that the drain-source breakdown voltage is lowered in this mode
Switching Time Test Circuit
(a) Test circuit
0
−2.5
V
10
μs
V
DD
OUT
V
DD
=
−10
V
R
G
=
4.7
Ω
Duty
≤
1%
V
IN
: t
r
, t
f
<
5 ns
Common source
Ta
=
25°C
(b) V
IN
0V
90%
10%
IN
R
G
−2.5
V
V
DS (ON)
90%
10%
t
r
t
on
(c) V
OUT
V
DD
t
f
t
off
Precaution
V
th
can be expressed as voltage between gate and source when low operating current value is I
D =
-
1mA for this
product. For normal switching operation, V
GS (on)
requires higher voltage than V
th
and V
GS (off)
requires lower
voltage than V
th
.(Relationship can be established as follows: V
GS (off)
<
V
th
<
V
GS (on)
)
Please take this into consideration for using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects
that come into direct contact with devices should be made of antistatic materials.
Thermal resistance R
th (ch-a)
and power dissipation P
D
vary depending on board material, board area, board
thickness and pad area. When using this device, please take heat dissipation into consideration
2
2014-03-01
SSM6J503NU
I
D
– V
DS
-10
VGS
=-4.5
V
-8
-1.5 V
-6
-2.5 V
-1.8 V
-100
Common Source
VDS
=
-3 V
Pulse test
I
D
– V
GS
-10
(A)
(A)
Drain current
I
D
-1
-0.1
Ta
=
100 °C
-0.01
−25
°C
-0.001
Drain current
I
D
-4
-2
0
Common Source
Ta
=
25 °C
Pulse test
0
-0.2
-0.4
-0.6
-0.8
-1
25 °C
-0.0001
0
-0.5
-1.0
-1.5
-2.0
Drain–source voltage
V
DS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– V
GS
140
120
ID = -0.5 A
Common Source
Pulse test
140
120
R
DS (ON)
– V
GS
ID = -2.5 A
Common Source
Pulse test
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
80
60
40
Ta
=
100 °C
25 °C
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
80
60
25 °C
40
Ta
=
100 °C
20
0
−
25 °C
0
-2
-4
-6
-8
20
−
25 °C
0
0
-2
-4
-6
-8
Gate–source voltage
V
GS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– I
D
140
120
140
Common Source
Ta = 25°C
-1.5 V
120
Common Source
Pulse test
R
DS (ON)
– Ta
Drain–source ON-resistance
R
DS (ON)
(mΩ)
Drain–source ON-resistance
R
DS (ON)
(mΩ)
Pulse test
100
80
100
-1.5 A / -1.8 V
-2.5 A / -2.5 V
ID
=
-0.5 A / VGS
=
-1.5 V
80
60
40
60
40
20
0
-2.5 V
0
-2.0
-4.0
-6.0
-1.8 V
VGS
=
-4.5 V
20
0
−50
-3.0 A / -4.5 V
-8.0
-10.0
0
50
100
150
Drain current
I
D
(A)
Ambient temperature
Ta
(°C)
3
2014-03-01
SSM6J503NU
V
th
– Ta
Common Source
VDS = -3 V
ID = -1 mA
(S)
-1.0
|Y
fs
| – I
D
100
Common Source
30
VDS
=
-3 V
Ta
=
25 °C
Pulse test
10
V
th
(V)
-0.8
-0.6
Forward transfer admittance
Gate threshold voltage
|Y
fs
|
3.0
-0.4
1.0
-0.2
0.3
0
−50
0
50
100
150
0.1
-0.01
-0.1
-1
-10
-100
Ambient temperature
Ta
(°C)
Drain current
I
D
(A)
10000
5000
C – V
DS
-8
Dynamic Input Characteristic
(pF)
3000
Ciss
(V)
V
GS
-6
C
VDD
=
-10 V
VDD
=
-16 V
1000
500
300
Capacitance
Gate–source voltage
-4
100
50
30
Common Source
Ta
=
25 °C
f
=
1 MHz
VGS
=
0 V
-1
-10
Coss
Crss
-2
Common Source
ID
=
-4.0 A
Ta
=
25 °C
0
0
10
20
30
10
-0.1
-100
Drain–source voltage
V
DS
(V)
Total Gate Charge
Qg
(nC)
10000
toff
tf
t – I
D
Common Source
VDD = -10 V
VGS = 0 to -2.5 V
Ta = 25 °C
RG = 4.7Ω
I
DR
– V
DS
100
Common Source
VGS
=
0 V
Pulse test
D
I
DR
G
1
(A)
I
DR
10
(ns)
1000
100
Drain reverse current
S
Switching time
t
0.1
ton
10
tr
0.01
100 °C
0.001
0
25 °C
−25
°C
0.4
0.6
0.8
1.0
1.2
1
-0.001
-0.01
-0.1
-1
-10
0.2
Drain current
I
D
(A)
Drain–source voltage
V
DS
(V)
4
2014-03-01
SSM6J503NU
R
th
–
t
w
b
P
D
– Ta
1400
a: Mounted on FR4 board
(25.4mm
×
25.4mm
×
1.6mm , Cu Pad : 645 mm
2
)
b: Mounted on FR4 board
1200
(25.4mm
×
25.4mm
×
1.6mm , Cu Pad : 2.27mm
2
)
Rth (°C/W)
1000
Power dissipation P
D
(mW)
1000
a
800
Transient thermal impedance
100
a
600
b
400
200
10
Single pulse
a. Mounted on F4 board
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
1
0.001
b. Mounted on F4 board
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 2.27 mm )
0.01
0.1
1
t
w
10
100
1000
0
-40
-20
0
20
40
60
80
100
120 140
160
Pulse width
(s)
Ambient temperature
Ta
(°C)
5
2014-03-01
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