TN0620N3-G datasheet, PDF - EEWORLD Datasheet

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TN0620N3-G: Descriptionmosfet 200v 6ohm; CategoryDiscrete semiconductor The transistor; File Size444KB，5 Pages; ManufacturerSupertex; Environmental Compliance

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TN0620N3-G Overview

mosfet 200v 6ohm

TN0620N3-G Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	TO-92
package instruction	CYLINDRICAL, O-PBCY-T3
Contacts	3
Reach Compliance Code	compli
ECCN code	EAR99
Other features	LOW THRESHOLD
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	200 V
Maximum drain current (ID)	0.25 A
Maximum drain-source on-resistance	6 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)	35 pF
JEDEC-95 code	TO-92
JESD-30 code	O-PBCY-T3
JESD-609 code	e3
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	150 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
Package shape	ROUND
Package form	CYLINDRICAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	N-CHANNEL
Certification status	Not Qualified
surface mount	NO
Terminal surface	Matte Tin (Sn)
Terminal form	THROUGH-HOLE
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON
Base Number Matches	1

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TN0620

N-Channel Enhancement-Mode

Vertical DMOS FET

Features

►

Low threshold (1.6V max.)

High input impedance

Low input capacitance (110pF typical)

Fast switching speeds

Low on-resistance

Free from secondary breakdown

Low input and output leakage

Complementary N- and P-channel devices

General Description

This low threshold, enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven, silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and the high input

impedance and positive temperature coefﬁcient inherent

in MOS devices. Characteristic of all MOS structures, this

device is free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

very low threshold voltage, high breakdown voltage, high

input impedance, low input capacitance, and fast switching

speeds are desired.

Applications

►

Logic level interfaces - ideal for TTL and CMOS

Solid state relays

Battery operated systems

Photo voltaic drives

Analog switches

General purpose line drivers

Telecom switches

Ordering Information

Device

TN0620

Package Option

TO-92

TN0620N3-G

DSS

/BV

DGS

(V)

DS(ON)

(max)

(Ω)

D(ON)

(min)

(A)

GS(th)

(max)

(V)

200

6.0

1.0

1.6

-G indicates package is RoHS compliant (‘Green’)

Pin Conﬁgurations

Absolute Maximum Ratings

Parameter

Drain-to-source voltage

Drain-to-gate voltage

Gate-to-source voltage

Operating and storage temperature

Soldering temperature*

Value

DSS

DGS

±20V

-55

C to +150

300

TO-92 (N3)

SOURCE

GATE

DRAIN

Product Marking

0 6 2 0

YYWW

YY = Year Sealed

WW = Week Sealed

= “Green” Packaging

TO-92 (N3)

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

Distance of 1.6mm from case for 10 seconds.

●

1235 Bordeaux Drive, Sunnyvale, CA 94089

●

Tel: 408-222-8888

●

www.supertex.com

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