M392T2950CZA-D5 datasheet, PDF

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M392T2950CZA-D5: DescriptionCache DRAM Module, 128MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size598KB，27 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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M392T2950CZA-D5 Overview

Cache DRAM Module, 128MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240

M392T2950CZA-D5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1126060107
package instruction	DIMM, DIMM240,40
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH; WD-MAX
Maximum clock frequency (fCLK)	267 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
JESD-609 code	e3
length	133.35 mm
memory density	9663676416 bit
Memory IC Type	CACHE DRAM MODULE
memory width	72
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	18.45 mm
self refresh	YES
Maximum standby current	0.664 A
Maximum slew rate	4.67 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4 mm

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512MB, 1GB, 2GB Registered DIMMs

DDR2 SDRAM

DDR2 Registered SDRAM MODULE

240pin Registered Module based on 512Mb C-die

72-bit ECC

60FBGA with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 27

Rev. 1.6 Dec. 2006

512MB, 1GB, 2GB Registered DIMMs

Table of Contents

DDR2 SDRAM

1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4

2.0 Features ........................................................................................................................................ 4

3.0 Address Configuration ................................................................................................................4

4.0 Pin Configurations (Front side/Back side) .................................................................................5

5.0 Pin Description .............................................................................................................................5

6.0 Input/Output Function Description .............................................................................................6

7.0 Functional Block Diagram............................................................................................................7

7.1 512MB, 64Mx72 Module (M393T6553CZ3 / M393T6553CZA / M392T6553CZA)

..................................... 7

.......................................8

7.3 1GB, 128Mx72 Module (M393T2950CZ3 / M393T2950CZA / M392T2950CZA)

........................................9

7.2 1GB, 128Mx72 Module (M393T2953CZ3 / M393T2953CZA / M392T2953CZA)

7.4 2GB, 256Mx72 Module (M393T5750CZ3 / M393T5750CZA)

...............................................................10

8.0 Absolute Maximum DC Ratings ................................................................................................11

9.0 AC & DC Operating Conditions .................................................................................................11

9.1 Operating Temperature Condition

................................................................................................12

9.2 Input DC Logic Level

..................................................................................................................12

9.3 Input AC Logic Level

..................................................................................................................12

9.4 AC Input Test Conditions

............................................................................................................12

10.0 IDD Specification Parameters Definition ................................................................................13

11.0 Operating Current Table(TA=0°C, VDD= 1.9V) .......................................................................14

11.1 M393T6553CZ3 / M393T6553CZA / M392T6553CZA

........................................................................14

11.2 M393T6553CZ3 / M393T6553CZA / M392T6553CZA - considering Register and PLL current value

........14

11.3 M393T2953CZ3 / M393T2953CZA / M392T2953CZA

........................................................................15

11.4 M393T2953CZ3 / M393T2953CZA / M392T2953CZA - considering Register and PLL current value

........15

11.5 M393T2950CZ3 / M393T2950CZA / M392T2950CZA

........................................................................16

11.6 M393T2950CZ3 / M393T2950CZA / M392T2950CZA - considering Register and PLL current value

........16

11.7 M393T5750CZ3 / M393T5750CZA

.................................................................................................17

11.8 M393T5750CZ3 / M393T5750CZA - considering Register and PLL current value

................................17

12.0 Input/Output Capacitance .......................................................................................................18

13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400..................................... 19

13.1 Refresh Parameters by Device Density

........................................................................................ 19

13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

.............................................19

13.3 Timing Parameters by Speed Grade

............................................................................................19

14.0 Physical Dimensions ............................................................................................................... 21

14.1 64Mbx8 based 64Mx72 Module (1 Rank)

.......................................................................................21

14.2 64Mbx8 based 64Mx72 Module (1 Rank)

...................................................................................... 22

14.3 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)

....................................................................23

14.4 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)

....................................................................24

14.5 128Mbx4 based 256Mx72 Module (2 Ranks)

..................................................................................25

15.0 240 Pin DDR2 Registered DIMM Clock Topology ..................................................................26

2 of 27

Rev. 1.6 Dec. 2006

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