74HC74; 74HCT74
Rev. 7 — 13 September 2021
Dual D-type flip-flop with set and reset; positive edge-trigger
Product data sheet
1. General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual
data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs.
Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock
transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock
input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp
diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2. Features and benefits
•
•
•
•
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Input levels:
•
For 74HC74: CMOS level
•
For 74HCT74: TTL level
Symmetrical output impedance
High noise immunity
Balanced propagation delays
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC74D
74HCT74D
74HC74PW
74HCT74PW
74HC74BQ
74HCT74BQ
-40 °C to +125 °C
DHVQFN14
-40 °C to +125 °C
TSSOP14
-40 °C to +125 °C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
Nexperia
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
4. Functional diagram
4
1SD
SD
D
CP
FF
Q
2
3
1D
1CP
1Q
5
Q
1Q
6
4 10
1SD 2SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
SD
Q
FF
Q
RD
1RD 2RD
1 13
mna418
4
3
2
1Q
2Q
1Q
2Q
5
9
6
8
S
C1
1D
R
5
6
RD
1
10
1RD
2SD
SD
D
CP
FF
Q
1
10
11
12
13
12
2D
2CP
2Q
9
S
C1
1D
R
mna419
9
8
11
Q
2Q
8
RD
13
2RD
mna420
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Functional diagram
Q
C
C
C
C
D
C
RD
SD
CP
C
C
C
C
Q
C
mna421
Fig. 4.
Logic diagram for one flip-flop
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 September 2021
2 / 17
Nexperia
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1. Pinning
74HC74
74HCT74
1RD
2
3
4
5
6
7
GND
2Q
8
GND
(1)
1
terminal 1
index area
1D
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
2Q
74HC74
74HCT74
1RD
1D
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
aaa-003908
1CP
1SD
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
8
2Q
2Q
1Q
1Q
aaa-003909
Transparent top view
Fig. 5.
Pin configuration for SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 6.
Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
complement output
ground (0 V)
complement output
output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 September 2021
3 / 17
Nexperia
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
nSD
L
H
L
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
Output
nQ
H
L
H
nQ
L
H
H
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑ = LOW-to-HIGH transition; Q
n+1
= state after the next LOW-to-HIGH CP transition.
Input
nSD
H
H
nRD
H
H
nCP
↑
↑
nD
L
H
Output
nQ
n+1
L
H
nQ
n+1
H
L
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to (V
CC
+ 0.5 V)
Min
-0.5
-
-
-
-
-100
-65
[1]
-
Max
+7
±20
±20
±25
+100
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
For SOT108-1 (SO14) package: P
tot
derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: P
tot
derates linearly with 9.6 mW/K above 98 °C.
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 September 2021
4 / 17
Nexperia
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-40
-
-
-
74HC74
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
-40
-
-
-
74HCT74
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
T
amb
= -40 °C to +85 °C
Min
74HC74
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
V
I
= V
IH
or V
IL
HIGH-level
output voltage
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
V
I
= V
IH
or V
IL
LOW-level
output voltage
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND; V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
3.84
5.34
-
-
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
4.32
5.81
0.15
0.16
-
-
3.5
-
-
-
0.5
1.35
1.8
-
-
0.33
0.33
±1.0
40
-
1.5
3.15
4.2
-
-
-
3.7
5.2
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
0.4
0.4
±1.0
80
-
V
V
V
V
V
V
V
V
V
V
μA
μA
pF
Typ
[1]
Max
T
amb
= -40 °C
to +125 °C
Min
Max
Unit
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
74HCT74
V
IH
V
IL
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
V
V
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 13 September 2021
5 / 17
Microcontroller MCU
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