Features
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Up to 2 Gsps Sampling Rate
Power Consumption: 4.6 W
500 mVpp Differential 100
Ω
or Single-ended 50
Ω (±2
%) Analog Inputs
Differential 100
Ω
or Single-ended 50
Ω
Clock Inputs
ECL or LVDS Output Compatibility
50
Ω
Differential Outputs with Common Mode not Dependent on Temperature
ADC Gain Adjust
Sampling Delay Adjust
Offset Control Capability
Data Ready Output with Asynchronous Reset
Out-of-range Output Bit
Selectable Decimation by 32 Functions
Gray or Binary Selectable Output Data; NRZ Output Mode
Pattern Generator Output (for Acquisition System Monitoring)
Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected)
CBGA 152 Cavity Down Hermetic Package
CBGA Package Evaluation Board TSEV83102G0BGL
Companion Device: DMUX 8-/10-bit 1:4/1:8 2 Gsps TS81102G0
10-bit 2 Gsps
ADC
TS83102G0B
Performance
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3.3 GHz Full Power Input Bandwidth (-3 dB)
Gain Flatness: ± 0.2 dB (from DC up to 1.5 GHz)
Low Input VSWR: 1.2 Max from DC to 2.5 GHz
SFDR = -59 dBc; 7.6 Effective Bits at F
S
= 1.4 Gsps, F
IN
= 700 MHz [-1 dBFS]
SFDR = -53 dBc; 7.1 Effective Bits at Fs = 1.4 Gsps, F
IN
= 1950 MHz [-1 dBFS]
SFDR = -54 dBc; 6.5 Effective Bits at F
S
= 2 Gsps, F
IN
= 2 GHz [-1 dBFS]
Low Bit Error Rate (10
-12
) at 2 Gsps
Application
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Direct RF Down Conversion
Wide Band Satellite Receiver
High-speed Instrumentation
High-speed Acquisition Systems
High-energy Physics
Automatic Test Equipment
Radar
Screening
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Temperature Range for Packaged Device:
– “C” grade: 0° C < Tc; Tj < 90° C
– “V” grade: -20° C < Tc; Tj < 110° C
Standard Die Flow (upon Request)
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Description
The TS83102G0B is a monolithic 10-bit analog-to-digital converter, designed for digi-
tizing wide bandwidth analog signals at very high sampling rates of up to 2 Gsps. It
uses an innovative architecture, including an on-chip Sample and Hold (S/H). The
3.3 GHz full power input bandwidth and band flatness performances enable the digitiz-
ing of high IF and large bandwidth signals.
2101D–BDC–06/04
Figure 1.
Simplified Block Diagram
PGEB
Sample &Hold
VIN
VINB
50
50
B/GB
OR
ORB
Analog Quantizer
D9
D9B
Logic block
D0
D0B
DR
DRB
GA
CLK
CLKB
50
50
SDA
Clock generation
SDA
DECB/
DIODE
DRRB
Functional Description
The TS83102G0B is a 10-bit 2 Gsps ADC. The device includes a front-end master/slave Track
and Hold stage (Sample and Hold), followed by an analog encoding stage (Analog Quantizer),
which outputs analog residues resulting from analog quantization. Successive banks of
latches regenerate the analog residues into logical levels before entering an error correction
circuit and resynchronization stage, followed by 50
Ω
differential output buffers.
The TS83102G0B works in a fully differential mode from analog inputs to digital outputs. A dif-
ferential Data Ready output (DR/DRB) is available to indicate when the outputs are valid and
an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the
first acquisition.
The control pin B/GB (A11 of the CBGA package) is provided to select either a binary or gray
data output format. The gain control pin GA (R9 of the CBGA package) is provided to adjust
the ADC gain transfer function.
A Sampling Delay Adjust function (SDA) may be used to ease the interleaving of ADCs.
A pattern generator is integrated on the chip for debug or acquisition setup. This function is
activated through the PGEB pin (A9 of the CBGA package).
An Out-of-range bit (OR/ORB) indicates when the input overrides 0.5 Vpp.
A selectable decimation by 32 functions is also available for enhanced testability coverage
(A10 of the CBGA package), along with the die junction temperature monitoring function.
The TS83102G0B uses only vertical isolated NPN transistors together with oxide isolated pol-
ysilicon resistors, which allows enhanced radiation tolerance (over 100 kRad (Si) total dose
expected tolerance).
2
TS83102G0B
2101D–BDC–06/04
TS83102G0B
Specification
Absolute Maximum Ratings
Parameter
Positive supply voltage
Digital negative supply voltage
Digital positive supply voltage
Negative supply voltage
Maximum difference between negative
supply voltages
Analog input voltages
Maximum difference between VIN and VINB
Clock input voltage
Maximum difference between VCLK and
VCLKB
Static input voltage
Digital input voltage
Digital output voltage
Junction temperature
Note:
Symbol
V
CC
D
VEE
V
PLUSD
V
EE
D
VEE
to V
EE
V
IN
or V
INB
V
IN
- V
INB
V
CLK
or V
CLKB
V
CLK
- V
CLKB
V
D
V
D
V
O
T
J
GA, SDA
SDAEN, DRRB, B/GB,
PGEB, DECB
Comments
Value
GND to 6.0
GND to -5.7
GND - 1.1 to 2.5
GND to -5.5
0.3
-1.5 to 1.5
-1.5 to 1.5
-1 to 1
-1 to 1
-5 to 0.8
-5 to 0.8
V
PLUSD
min operating -2.2 to
V
PLUSD
max operating + 0.8
130
Unit
V
V
V
V
V
V
V
V
Vpp
V
V
V
°C
Absolute maximum ratings are short term limiting values (referenced to GND = 0V), to be applied individually, while other
parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. All inte-
grated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropriate
handling or storage could range from performance degradation to complete failure.
Recommended Conditions of Use
Parameter
Positive supply voltage
Symbol
V
CC
Differential ECL output
compatibility
Positive digital supply
voltage
V
PLUSD
LVDS output compatibility
Comments
Min
4.75
- 0.9
1.375
Grounded
(1)
Maximum operating VPLUSD
Negative supply voltages
Differential analog input
voltage (full-scale)
Clock input power level
(ground common mode)
V
EE
, D
VEE
V
IN
, V
INB
V
IN
- V
INB
P
CLK
, P
CLKB
50
Ω
differential or single-ended
50
Ω
single-ended clock input or
100
Ω
differential clock
(recommended)
- 5.25
±113
450
-4
- 5.0
±125
500
0
1.7
- 4.75
±137
550
4
V
V
mV
mVpp
dBm
Typ
5
- 0.8
1.45
Max
5.25
- 0.7
1.525
Unit
V
V
V
3
2101D–BDC–06/04
Recommended Conditions of Use (Continued)
Parameter
Operating Temperature
Range
Storage Temperature
Lead Temperature
Note:
Tstg
Tlead
Symbol
Comments
Commercial "C" grade
Industrial "V" grade
Min
Typ
Max
Unit
°C
°C
°C
0°C < T
C
; T
J
< 90°C
-20°C < T
C
; T
J
< 110°C
-65 to 150
300
1.
ADC performances are independent on V
PLUSD
common mode voltage and performances are guaranteed in the
limits of the specified V
PLUSD
range (from -0.9V to 1.7V).
Electrical Operating Characteristics
V
CC
= 5V ; V
PLUSD
= 0V (unless otherwise specified). ADC performances are independent of V
PLUSD
common mode
voltage and performances are guaranteed within the limits of the specified V
PLUSD
range (from -0.9V to 1.7V);
V
EE
= D
VEE
= -5V; V
IN
- V
INB
= 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Resolution
Power Requirements
Positive supply voltage
- analog
- digital (ECL)
- digital (LVDS)
Positive supply current
- analog
- digital
Negative supply voltage
- analog
- digital
Negative supply current
- analog
- digital
Power dissipation
- ECL
- LVDS
Analog Inputs
Full-scale input voltage range (differential mode)
(0 V common mode voltage)
Full-scale input voltage range (single-ended input
option)
(0 V common mode voltage)
4
4
4
4
V
IN,
V
INB
V
IN,
- 250
V
INB
0
250
mV
- 125
- 125
125
125
mV
mV
mV
1
1
4
1
1
1
1
1
1
1
4
V
CC
V
PLUSD
V
PLUSD
I
VCC
I
VPLUSD
V
EE
D
VEE
V
EE
I
DVEE
-5.25
-5.25
4.75
5
- 0.8
1.45
138
154
-5
-5
615
160
4.6
5.0
5.25
V
V
V
mA
mA
V
V
mA
mA
W
W
Test
Level
Symbol
Min
Typ
10
Max
Unit
Bits
205
200
-4.75
-4.75
750
200
5.2
5.7
P
D
4
TS83102G0B
2101D–BDC–06/04
TS83102G0B
Electrical Operating Characteristics (Continued)
V
CC
= 5V ; V
PLUSD
= 0V (unless otherwise specified). ADC performances are independent of V
PLUSD
common mode
voltage and performances are guaranteed within the limits of the specified V
PLUSD
range (from -0.9V to 1.7V);
V
EE
= D
VEE
= -5V; V
IN
- V
INB
= 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Analog input power level (50
Ω
single-ended)
Analog input capacitance (die)
Input leakage current
Input resistance
- single-ended
- differential
Clock Inputs
Logic common mode compatibility for clock inputs
Clock inputs common voltage range (V
CLK
or V
CLKB
)
(DC coupled clock input)
AC coupled for LVDS compatibility (common mode
1.2V)
Clock input power level (low-phase noise sinewave
input)
50
Ω
single-ended or 100
Ω
differential
Clock input swing (single ended; with CLKB = 50
Ω
to GND)
Clock input swing (differential voltage) - on each
clock input
Clock input capacitance (die)
Clock input resistance
- single-ended
- differential ended
Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB, DRRB)
- logic low
- logic high
Digital Inputs (DRRB Only)
Logic Compatibility
- logic low
- logic high
4
V
IL
V
IH
-1.810
-1.165
Negative ECL
-1.625
-0.880
V
V
4
V
IL
V
IH
-5
-2
-3
0
V
V
Differential ECL to LVDS
Test
Level
4
4
4
4
4
Symbol
P
IN
C
IN
I
IN
R
IN
R
IN
49
98
Min
Typ
-2
0.3
10
50
100
51
102
Max
Unit
dBm
pF
µA
Ω
Ω
4
V
CM
-1.2
0
0.3
V
4
P
CLK
-4
0
4
dBm
4
4
4
V
CLK
V
CLK
V
CLKB
C
CLK
R
CLK
R
CLK
±200
±141
±320
±226
0.3
±500
±354
mV
mV
pF
45
90
50
100
55
110
Ω
Ω
5
2101D–BDC–06/04
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