EEWORLDEEWORLDEEWORLD

Part Number

Search

EP3SL340H1152C2N

Description
fpga - field programmable gate array fpga - stratix iii 13500 labs 744 ios
CategoryProgrammable logic devices    Programmable logic   
File Size191KB,16 Pages
ManufacturerAltera (Intel)
Environmental Compliance
Download Datasheet Parametric View All

EP3SL340H1152C2N Online Shopping

Suppliers Part Number Price MOQ In stock  
EP3SL340H1152C2N - - View Buy Now

EP3SL340H1152C2N Overview

fpga - field programmable gate array fpga - stratix iii 13500 labs 744 ios

EP3SL340H1152C2N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerAltera (Intel)
Parts packaging codeBGA
package instructionLEAD FREE, HBGA-1152
Contacts1152
Reach Compliance Code_compli
ECCN code3A001.A.7.A
Other featuresIT CAN ALSO OPERATE FROM 1.05 TO 1.15V SUPPLY
maximum clock frequency800 MHz
JESD-30 codeS-PBGA-B1152
JESD-609 codee1
length40 mm
Humidity sensitivity level4
Number of entries744
Number of logical units337500
Output times744
Number of terminals1152
Maximum operating temperature85 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1152,34X34,40
Package shapeSQUARE
Package formGRID ARRAY
power supply1.2/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.9 mm
Maximum supply voltage0.94 V
Minimum supply voltage0.86 V
Nominal supply voltage0.9 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width40 mm
1. Stratix III Device Family Overview
SIII51001-1.8
The Stratix
®
III family provides one of the most architecturally advanced,
high-performance, low-power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Altera’s innovative
Programmable Power Technology, which provides the ability to turn on the
performance where needed and turn down the power consumption for blocks not in
use. Selectable Core Voltage and the latest in silicon process optimizations are also
employed to deliver the industry’s lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III
FPGA family offers two variants optimized to meet different application needs:
The Stratix III
L
family provides balanced logic, memory, and multiplier ratios for
mainstream applications.
The Stratix III
E
family is memory- and multiplier-rich for data-centric
applications.
Modular I/O banks with a common bank structure for vertical migration lend
efficiency and flexibility to the high-speed I/O. Package and die enhancements with
dynamic on-chip termination, output delay, and current strength control provide
best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a
programmable alternative to custom ASICs and programmable processors for
high-performance logic, digital signal processing (DSP), and embedded designs.
Stratix III devices include optional configuration bit stream security through volatile
or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where
ultra-high reliability is required, Stratix III devices include automatic error detection
circuitry to detect data corruption by soft errors in the configuration random-access
memory (CRAM) and user memory cells.
Features Summary
Stratix III devices offer the following features:
48,000 to 338,000 equivalent logic elements (LEs) ( refer to
Table 1–1)
2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM
block sizes to implement true dual-port memory and FIFO buffers
High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,
and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for
robust signal integrity
Programmable Power Technology, which minimizes power while maximizing
device performance
© March 2010
Altera Corporation
Stratix III Device Handbook, Volume 1
Excuse me, why is the digital tube display not bright enough?
I use 6 common cathode digital tubes. The P1 port connects to each segment of the digital tube, and the P0 port controls the on/off of the digital tube. I have connected it like this: A 9-pin 5.1K sin...
pangxie Embedded System
I want to make a three-cell lithium battery protection circuit board
Does anyone have relevant information? . . ....
WTT001 Suggestions & Announcements
【ufun learning】Match 12M external crystal by modifying SystemInit
[size=5]Previous words: [/size] The default external clock of stm32f103RC in version 3.5 of the library function is 8MHZ. Generally, we have a maximum clock of 72MHZ. If the external clock is 12MHZ, h...
freeelectron stm32/stm8
error LNK2019: unresolved external symbol...problem!
I am making an audio plug-in and calling the functions of the amr standard library. However, the following problem occurs when associating the amr-nb standard library. Can someone please tell me how t...
topcool99 Embedded System
DC power supply control board system with single chip microcomputer as the core
This paper introduces a DC power supply control board system with single-chip microcomputer controlling thyristor trigger pulse as the core. The system realizes the synchronous generation, phase shift...
sairvee MCU
Xilinx Pinout
I would like to ask everyone, how do you match pins in text form in ISE?...
geek1044233591 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1682  1576  2488  19  1840  34  32  51  1  38 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号