Per Channel PCS/FPGA Interface Ports................................................................................................... 1-4
Using this Data Sheet ............................................................................................................................... 1-7
SERDES Port Description.................................................................................................................................. 2-6
Transmit Data Skew................................................................................................................................ 2-23
Status Interrupt Registers ................................................................................................................................ 2-27
Receive CDR Loss of Lock Interrupt Usage .................................................................................................... 2-27
SERDES High Speed Data Transmitter.................................................................................................. 2-31
SERDES High Speed Data Receiver...................................................................................................... 2-33
Interfacing to Reference Clock CML Buffers.................................................................................................... 2-36
SERDES Power ............................................................................................................................................... 2-37
SERDES Power Supply Sequencing Requirements............................................................................... 2-38
SERDES Power Supply Requirements............................................................................................................ 2-38
SERDES Power Supply Package Requirements............................................................................................. 2-38
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
i
Lattice Semiconductor
Table of Contents
LatticeSC/M Family flexiPCS Data Sheet
8-bit SERDES Only Auto-Configuration Example ..................................................................................... 3-4
10-bit SERDES Only Register Settings..................................................................................................... 3-5
10-bit SERDES Only Auto-Configuration Example ................................................................................... 3-6
8-bit SERDES Only Mode .................................................................................................................................. 3-6
8-bit SERDES Only Mode Pin Description......................................................................................................... 3-8
8-bit SERDES Only Mode Detailed Description................................................................................................. 3-9
Control & Status ...................................................................................................................................... 3-16
10-bit SERDES Only Mode .............................................................................................................................. 3-16
10-bit SERDES Only Mode Pin Description..................................................................................................... 3-18
10-bit SERDES Only Mode Detailed Description............................................................................................. 3-19
Control & Status ...................................................................................................................................... 3-26
Control & Status ...................................................................................................................................... 4-32
Status Interrupt Registers ....................................................................................................................... 4-33
Control & Status ...................................................................................................................................... 5-25
Status Interrupt Registers ....................................................................................................................... 5-26
Control & Status ...................................................................................................................................... 6-23
Status Interrupt Registers ....................................................................................................................... 6-23
Control & Status ...................................................................................................................................... 7-25
Status Interrupt Registers ....................................................................................................................... 7-26
Control & Status ...................................................................................................................................... 8-21
Control & Status ...................................................................................................................................... 8-37
Status Interrupt Registers ....................................................................................................................... 8-38
iii
Lattice Semiconductor
Table of Contents
LatticeSC/M Family flexiPCS Data Sheet
Serial RapidIO Mode ........................................................................................................................... 9-1
Serial RapidIO Register Settings .............................................................................................................. 9-4
Serial RapidIO Auto-Configuration Example............................................................................................. 9-5
Serial RapidIO Mode.......................................................................................................................................... 9-6
1x Serial RapidIO Mode Pin Descriptions .......................................................................................................... 9-8
Serial RapidIO Mode Detailed Description......................................................................................................... 9-9
Control & Status ...................................................................................................................................... 9-19
4x Serial RapidIO Operation ............................................................................................................................ 9-20
4x Serial RapidIO Operation Pin Description ................................................................................................... 9-22
4x Serial RapidIO Operation Detailed Description ........................................................................................... 9-23
Control & Status ...................................................................................................................................... 9-32
Status Interrupt Registers ....................................................................................................................... 9-33
Control & Status .................................................................................................................................... 10-25
Status Interrupt Registers ..................................................................................................................... 10-26
Alignment Within A Quad ................................................................................................................................. 11-4
Alignment Between Quads............................................................................................................................. 11-13
Alignment Between Two Devices................................................................................................................... 11-19
Synchronization of Aligned Channels Across Two Devices.................................................................. 11-20
Status Interrupt Registers ..................................................................................................................... 11-21
PRBS Generator and Checker......................................................................................................................... 12-4
[i=s] This post was last edited by paulhyde on 2014-9-15 03:50 [/i] Experts please come in and help us win the national competition and give the corresponding reward...
[size=4][color=#0000ff]Introduction to Symbian System[/color][color=red]Edit by:UOL[/color] Main source of information: Symbian official website[/size][url=http://www.symbian.com/][size=4][color=#0000...
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