Features
•
High Performance, Low Power 32-bit AVR
®
Microcontroller
Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
Built-in Floating-Point Processing Unit (FPU)
Read-Modify-Write Instructions and Atomic Bit Manipulation
Performing 1.49 DMIPS / MHz
• Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)
• Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State)
– Memory Protection Unit
Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 16 Peripheral DMA Channels Improves Speed for Peripheral Communication
Internal High-Speed Flash
– 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions
– Single Cycle Access up to 33 MHz
– FlashVault
™
Technology Allows Pre-programmed Secure Library Support for End
User Applications
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash), 16 Kbytes (64 KB
Flash)
– 4 Kbytes on the Multi-Layer Bus System (HSB RAM)
External Memory Interface on AT32UC3C0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
System Functions
– Power and Clock Manager
– Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators
– One 32 KHz and Two Multipurpose Oscillators
– Clock Failure detection
– Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or
CAN Frequency
Windowed Watchdog Timer (WDT)
Asynchronous Timer (AST) with Real-Time Clock Capability
– Counter or Calendar Mode Supported
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
Universal Serial Bus (USB)
– Device 2.0 and Embedded Host Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
One 2-channel Controller Area Network (CAN)
– CAN2A and CAN2B protocol compliant, with high-level mailbox system
– Two independent channels, 16 Message Objects per Channel
–
–
–
–
•
32-bit AVR
®
Microcontroller
AT32UC3C0512C
AT32UC3C0256C
AT32UC3C0128C
AT32UC3C064C
AT32UC3C1512C
AT32UC3C1256C
AT32UC3C1128C
AT32UC3C164C
AT32UC3C2512C
AT32UC3C2256C
AT32UC3C2128C
AT32UC3C264C
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32117D–AVR–01/12
AT32UC3C
•
One 4-Channel 20-bit Pulse Width Modulation Controller (PWM)
– Complementary outputs, with Dead Time Insertion
– Output Override and Fault Protection
Two Quadrature Decoders
One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC)
– Dual Sample and Hold Capability Allowing 2 Synchronous Conversions
– Single-Ended and Differential Channels, Window Function
Two 12-bit Digital-To-Analog Converters (DAC), with Dual Output Sample System
Four Analog Comparators
Six 16-bit Timer/Counter (TC) Channels
– External Clock Inputs, PWM, Capture and Various Counting Capabilities
One Peripheral Event Controller
– Trigger Actions in Peripherals Depending on Events Generated from Peripherals or from Input Pins
– Deterministic Trigger
– 34 Events and 22 Event Actions
Five Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independent Baudrate Generator, Support for SPI, LIN, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
One Inter-IC Sound (I2S) Controller
– Compliant with I2S Bus Specification
– Time Division Multiplexed mode
Three Master and Three Slave Two-Wire Interfaces (TWI), 400kbit/s I
2
C-compatible
QTouch
®
Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch
®
and QMatrix
®
Acquisition
On-Chip Non-intrusive Debug System
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
– aWire
™
single-pin programming trace and debug interface muxed with reset pin
– NanoTrace
™
provides trace capabilities through JTAG or aWire interface
3 package options
– 64-pin QFN/TQFP (45 GPIO pins)
– 100-pin TQFP (81 GPIO pins)
– 144-pin LQFP (123 GPIO pins)
Two operating voltage ranges:
– Single 5V Power Supply
– Single 3.3V Power Supply
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2
32117D–AVR-01/12
AT32UC3C
1. Description
The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC
processor running at frequencies up to 66 MHz. AVR32UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems. Using the
Secure Access Unit (SAU) together with the MPU provides the required security and integrity.
Higher computation capabilities are achievable either using a rich set of DSP instructions or
using the floating-point instructions.
The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3C0 derivatives.
The Memory Direct Memory Access controller (MDMA) enables transfers of block of data from
memories to memories without processor involvement.
The Peripheral Direct Memory Access (PDCA) controller enables data transfers between periph-
erals and memories without processor involvement. The PDCA drastically reduces processing
overhead when transferring continuous and large data streams.
The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.
The FlashVault technology allows secure libraries to be programmed into the device. The secure
libraries can be executed while the CPU is in Secure State, but not read by non-secure software
in the device. The device can thus be shipped to end custumers, who are able to program their
own code into the device, accessing the secure libraries, without any risk of compromising the
proprietary secure code.
The Power Manager improves design flexibility and security. Power monitoring is supported by
on-chip Power-On Reset (POR), Brown-Out Detectors (BOD18, BOD33, BOD50). The CPU
runs from the on-chip RC oscillators, the PLLs, or the Multipurpose Oscillators. The Asynchro-
nous Timer (AST) combined with the 32 KHz oscillator keeps track of the time. The AST can
operate in counter or calendar mode.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The PWM module provides four channels with many configuration options including polarity,
edge alignment and waveform non overlap control. The PWM channels can operate indepen-
dently, with duty cycles set independently from each other, or in interlinked mode, with multiple
channels updated at the same time. It also includes safety feature with fault inputs and the ability
to lock the PWM configuration registers and the PWM pin assignment.
The AT32UC3C also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible CAN, USB and Ethernet MAC are available. The USART supports different communica-
tion modes, like SPI mode and LIN mode.
The Inter-IC Sound Controller (I2SC) provides a 5-bit wide, bidirectional, synchronous, digital
audio link with off-chip audio devices. The controller is compliant with the I2S bus specification.
3
32117D–AVR-01/12
AT32UC3C
The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time
thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device
like a USB Flash disk or a USB printer to be directly connected to the processor.
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module
provides on-chip solutions for network-connected devices.
The Peripheral Event Controller (PEVC) allows to redirect events from one peripheral or from
input pins to another peripheral. It can then trigger, in a deterministic time, an action inside a
peripheral without the need of CPU. For instance a PWM waveform can directly trigger an ADC
capture, hence avoiding delays due to software interrupt processing.
The AT32UC3C features analog functions like ADC, DAC, Analog comparators. The ADC inter-
face is built around a 12-bit pipelined ADC core and is able to control two independent 8-channel
or one 16-channel. The ADC block is able to measure two different voltages sampled at the
same time. The analog comparators can be paired to detect when the sensing voltage is within
or outside the defined reference window.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key
Suppression
®
(AKS
®
) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.
AT32UC3C integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control. The
Nanotrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin
aWire interface allows all features available through the JTAG interface to be accessed through
the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals.
4
32117D–AVR-01/12
AT32UC3C
2. Overview
2.1
Block diagram
Figure 2-1.
RESET_N
TDO
TCK
TDI
TMS
Block diagram
aWire
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
VBUS
D+
D-
ID
VBOF
AVR32UC CPU
NEXUS
CLASS 2+
OCD
MEMORY INTERFACE
LOCAL BUS
INTERFACE
LOCAL BUS
MEMORY PROTECTION UNIT
INSTR
INTERFACE
DATA
INTERFACE
64/32/16
KB SRAM
USB
INTERFACE
Flash
Controller
4 KB
HSB
RAM
CANIF
M
S
M
M
M
S
S
512/
256/
128/64
KB
Flash
RXLINE[0]
TXLINE[0]
RXLINE[1]
TXCAN[1]
HIGH SPEED
BUS MATRIX
S
M
S
PBB
M
M
W
R
EXTERNAL BUS INTERFACE
(SDRAM & STATIC MEMORY
CONTROLLER)
Memory
DMA
DMA
DATA[15..0]
ADDR[23..0]
NCS[3..0]
NRD
NWAIT
NWE0
NWE1
RAS
CAS
SDA10
SDCK
SDCKE
SDWE
M
CONFIGURATION
S
REGISTERS
HSB
BUS
S
M
COL,
CRS,
RXD[3..0],
RX_CLK,
RX_DV,
RX_ER,
TX_CLK
MDC,
TXD[3..0],
TX_EN,
TX_ER,
SPEED
MDIO
HSB
HSB-PB
BRIDGE C
PB
PERIPHERAL
DMA
CONTROLLER
HSB
PB
HSB-PB
BRIDGE A
PB
HSB-PB
BRIDGE B
ETHERNET
MAC
GENERAL PURPOSE IOs
USART4
supplied by VDDANA
ADCREF0/1
ADCIN[15..0]
ADCVREFP/N
SCK
MISO, MOSI
NPCS[3..0]
CLK[2..0]
ANALOG TO
DIGITAL
CONVERTER 0/1
SERIAL
PERIPHERAL
INTERFACE 0
TIMER/COUNTER 0
DMA
PA
PB
PC
PD
DSR, DTR, DCD, RI
RTS, CTS
CLK
TXD
RXD
RTS, CTS
CLK
TXD
RXD
PBA
USART1
PERIPHERAL EVENT
CONTROLLER
USART0
USART2
USART3
SERIAL
PERIPHERAL
INTERFACE 1
PBC
PAD_EVT
DMA
DMA
DMA
A[2..0]
B[2..0]
TWCK
TWD
EXTINT[8:1]
NMI
TWO-WIRE
INTERFACE 0/1
PULSE WIDTH
MODULATION
CONTROLLER
supplied by VDDANA
DIGITAL TO
ANALOG
CONVERTER 0/1
ANALOG
COMPARATOR
0A/0B/1A/1B
TWCK
TWD
TWALM
PWMH[3..0]
PWML[3..0]
EXT_FAULTS[1:0]
GENERAL PURPOSE IOs
DMA
DMA
DMA
DMA
RXD
TXD
CLK
RTS, CTS
SCK
MISO, MOSI
NPCS[3..0]
BCLK
IWS
ISDI
ISDO
MCLK
I2S INTERFACE
External Interrupt
Controller
POWER MANAGER
SLEEP
CONTROLLER
RESET
CONTROLLER
DMA
DMA
TWO-WIRE
INTERFACE 2
PA
PB
PC
PD
DMA
CLOCK
CONTROLLER
DAC0A/B
DAC1A/B
DACREF
GCLK[1..0]
AC0AP/N AC0BP/N
AC1AP/N AC1BP/N
AC0AOUT/AC0BOUT
AC1AOUT/AC1BOUT
RCSYS
RC8M
RC120M
XIN[1:0]
XOUT[1:0]
A[2..0]
TIMER/COUNTER 1
SYSTEM CONTROL
INTERFACE
B[2..0]
CLK[2..0]
OSC0 / OSC1
PLL0 / PLL1
QUADRATURE
DECODER
0/1
ASYNCHRONOUS
TIMER
FREQUENCY METER
QEPA
QEPB
QEPI
XIN32
XOUT32
32 KHz OSC
BODs (1.8V,
3.3V, 5V)
WATCHDOG
TIMER
5
32117D–AVR-01/12
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