EEWORLDEEWORLDEEWORLD

Part Number

Search

5SGXMA5K3F40I3N

Description
fpga - field programmable gate array fpga - stratix V GX 2304 labs 696 ios
CategoryProgrammable logic devices    Programmable logic   
File Size406KB,21 Pages
ManufacturerAltera (Intel)
Environmental Compliance
Download Datasheet Parametric View All

5SGXMA5K3F40I3N Online Shopping

Suppliers Part Number Price MOQ In stock  
5SGXMA5K3F40I3N - - View Buy Now

5SGXMA5K3F40I3N Overview

fpga - field programmable gate array fpga - stratix V GX 2304 labs 696 ios

5SGXMA5K3F40I3N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerAltera (Intel)
package instructionFBGA-1517
Reach Compliance Codecompliant
ECCN code3A001.A.7.A
JESD-30 codeS-PBGA-B1517
length40 mm
Configurable number of logic blocks18500
Number of entries696
Number of logical units490000
Output times696
Number of terminals1517
Maximum operating temperature100 °C
Minimum operating temperature-40 °C
organize18500 CLBS
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1517,39X39,40
Package shapeSQUARE
Package formGRID ARRAY
power supply0.85,1.5,2.5,2.5/3,1.2/3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage0.88 V
Minimum supply voltage0.82 V
Nominal supply voltage0.85 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width40 mm
2014.04.08
Stratix V Device Overview
Subscribe
Send Feedback
SV51001
Many of the Stratix
®
V devices and features are enabled in the Quartus
®
II software version 13.0. The
remaining devices and features will be enabled in future versions of the Quartus II software.
Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated
transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property
(IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices
optimized for:
• Bandwidth-centric applications and protocols, including PCI Express
®
(PCIe
®
) Gen3
• Data-intensive applications for 40G/100G and beyond
• High-performance, high-precision digital signal processing (DSP) applications
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of
applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk,
low-cost path to HardCopy
®
V ASICs.
Related Information
Stratix V Device Handbook: Known Issues
Lists the planned updates to the
Stratix V Device Handbook
chapters.
Upcoming Stratix V Device Features
Stratix V Family Variants
The Stratix V device family contains the GT, GX, GS, and E variants.
Stratix V GT
devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications that
require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communications
systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX
channels, respectively.
Stratix V GX
devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These
transceivers also support backplane and optical interface applications. These devices are optimized for high-
performance, high-bandwidth applications such as 40G/100G optical transport, packet processing, and
traffic management found in wireline, military communications, and network test equipment markets.
Stratix V GS
devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18 or
1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps data
rate capability. These transceivers also support backplane and optical interface applications. These devices
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
EEWORLD University - Keysight Two-Minute Mentor Season 1
Keysight Two-Minute Mentor Season 1 : https://training.eeworld.com.cn/course/4657Explain acquisition, triggering, coupling, noise, jitter, etc. in simple terms...
老白菜 Analog electronics
Negative power rails won't go away
[color=#a0522d]Background Negative power rails are used with major IC building blocks such as digital-to-analog converters (DACs), analog-to-digital converters (ADCs), operational amplifiers, and GaAs...
qwqwqw2088 Analogue and Mixed Signal
PIC16F877A AD Conversion
The AD conversion digital tube displays a decreasing value. Unplug the power supply and restart from 4.99 volts. The analog input is connected from the 5V regulator tube on the same board and connecte...
小灰 Microchip MCU
Discuss FPGA interview questions
Implement a clock generator using Verilog/ VHDL . The requirements are as follows: a . Realize 2-way and 4-way frequency division b . Make the skew of the two output clocks as small as possible c . Af...
eeleader FPGA/CPLD
The Definitive Guide to Visual Studio Code
This book introduces all aspects of Visual Studio Code from the basics to the depth, mainly including the core components of Visual Studio Code, usage tips, advanced applications, plug-in recommendati...
arui1999 Download Centre
My little speaker has arrived.
:loveliness: The small speaker I got as a reward from the forum has arrived two days ago. I was offline recently and didn’t have time to say hello. Haha, the speaker is quite unique. Thank you Linglon...
leijiayou Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 196  705  226  2083  153  4  15  5  42  14 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号