Freescale Semiconductor
Technical Data
DSP56303
Rev. 11, 2/2005
DSP56303
24-Bit Digital Signal Processor
16
6
6
3
Memory Expansion Area
Triple
Timer
HI08
ESSI
SCI
PrograM
RAM
4096
×
24
bits
(default)
PM_EB
X Data
RAM
2048
×
24
bits
(default)
XM_EB
Y Data
RAM
2048
×
24
bits
(default)
YM_EB
Peripheral
Expansion Area
Address
Generation
Unit
Six-Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
24-Bit
18
External
Address
Bus
Address
Switch
External
Bus
13
Interface
and Inst.
Cache Control
Control
External
Data Bus
Switch
24
The DSP56303 is intended
for use in telecommunication
applications, such as multi-
line voice/data/ fax
processing, video
conferencing, audio
applications, control, and
general digital signal
processing.
PIO_EB
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Internal
Data
Bus
Switch
EXTAL
XTAL
Clock
Generator
PLL
2
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
What’s New?
Data
Rev. 11 includes the following
changes:
•
Adds lead-free packaging and
part numbers.
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Data ALU
Power
Management
JTAG
OnCE™
5
DE
Figure 1.
DSP56303 Block Diagram
The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural
features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The
DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family
offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable
wireless, telecommunications, and multimedia products.
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.
Table of Contents
Data Sheet Conventions .......................................................................................................................................ii
Features...............................................................................................................................................................iii
Target Applications ............................................................................................................................................. iv
Product Documentation ......................................................................................................................................iv
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
Power ................................................................................................................................................................1-3
Ground ..............................................................................................................................................................1-3
Clock.................................................................................................................................................................1-4
External Memory Expansion Port (Port A) ......................................................................................................1-4
Interrupt and Mode Control ..............................................................................................................................1-7
Host Interface (HI08)........................................................................................................................................1-8
Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11
Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12
Serial Communication Interface (SCI) ...........................................................................................................1-14
Timers .............................................................................................................................................................1-15
JTAG and OnCE Interface ..............................................................................................................................1-16
Maximum Ratings.............................................................................................................................................2-1
Thermal Characteristics ....................................................................................................................................2-2
DC Electrical Characteristics............................................................................................................................2-2
AC Electrical Characteristics............................................................................................................................2-3
TQFP Package Description...............................................................................................................................3-2
TQFP Package Mechanical Drawing................................................................................................................3-9
MAP-BGA Package Description ....................................................................................................................3-10
MAP-BGA Package Mechanical Drawing .....................................................................................................3-18
Thermal Design Considerations........................................................................................................................4-1
Electrical Design Considerations......................................................................................................................4-2
Power Consumption Considerations.................................................................................................................4-3
PLL Performance Issues ...................................................................................................................................4-4
Input (EXTAL) Jitter Requirements .................................................................................................................4-5
Chapter 2
Specifications
2.1
2.3
2.4
2.5
Chapter 3
Packaging
3.1
3.2
3.3
3.4
Chapter 4
Design Considerations
4.1
4.2
4.3
4.4
4.5
Appendix A
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
“asserted”
“deasserted”
Examples:
Indicates a signal that is active when pulled low (For example, the
RESET
pin is active when
low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Signal State
PIN
True
Asserted
PIN
False
Deasserted
PIN
True
Asserted
PIN
False
Deasserted
Note:
Values for
V
IL
,
V
OL
,
V
IH
, and
V
OH
are defined by individual product specifications.
DSP56303 Technical Data, Rev. 11
ii
Freescale Semiconductor
Features
Table 1
lists the features of the DSP56303 device.
Table 1.
DSP56303 Features
Feature
Description
• 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24
×
24-bit parallel multiplier-accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals
are enabled
• 192
×
24-bit bootstrap ROM
• 8 K
×
24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
High-Performance
DSP56300 Core
Internal Peripherals
Internal Memories
Program RAM
Size
4096
×
24-bit
3072
×
24-bit
2048
×
24-bit
1024
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size
2048
×
24-bit
2048
×
24-bit
3072
×
24-bit
3072
×
24-bit
Y Data RAM
Size
2048
×
24-bit
2048
×
24-bit
3072
×
24-bit
3072
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
Switch Mode
disabled
disabled
enabled
enabled
External Memory
Expansion
• Data memory expansion to two 256 K
×
24-bit word memory spaces using the standard external address
lines
• Program memory expansion to one 256 K
×
24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
• Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
•
•
•
•
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Power Dissipation
Packaging
• 144-pin TQFP package in lead-free or lead-bearing versions
• 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
iii
Target Applications
Examples include:
•
•
•
•
Multi-line voice/data/fax processing
Video conferencing
Audio applications
Control
Product Documentation
The documents listed in
Table 2
are required for a complete description of the DSP56303 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2.
DSP56303 Documentation
Name
DSP56303
User’s Manual
Description
Detailed functional description of the DSP56303 memory configuration,
operation, and register programming
Order Number
DSP56303UM
DSP56300FM
See the DSP56303 product website
DSP56300 Family
Detailed description of the DSP56300 family processor core and instruction set
Manual
Application Notes
Documents describing specific applications or optimized device operation
including code examples
DSP56303 Technical Data, Rev. 11
iv
Freescale Semiconductor
Signals/Connections
1
The DSP56303 input and output signals are organized into functional groups as shown in
Table 1-1. Figure 1-1
diagrams the DSP56303 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Table 1-1.
DSP56303 Functional Signal Groupings
Number of Signals
Functional Group
TQFP
Power (V
CC
)
Ground (GND)
Clock
PLL
Address bus
Data bus
Bus control
Interrupt and mode control
Host interface (HI08)
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
OnCE/JTAG Port
Notes:
1.
2.
3.
4.
5.
Port B
2
Ports C and D
3
Port E
4
Port A
1
18
19
2
3
18
24
13
5
16
12
3
3
6
MAP-BGA
18
66
2
3
18
24
13
5
16
12
3
3
6
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
Port B signals are the HI08 port signals multiplexed with the GPIO signals.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
There are 2 signal connections in the TQFP package and 7 signal connections in the MAP-BGA package that are not used.
These are designated as no connect (NC) in the package description (see
Chapter 3).
Note:
This chapter refers to a number of configuration registers used to select individual multiplexed signal
functionality. Refer to the
DSP56303 User’s Manual
for details on these configuration registers.
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
1-1
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