PIC16C63A/65B/73B/74B
PIC16C63A/65B/73B/74B Data Sheet Errata
The PIC16C63A/65B/73B/74B parts you have received
conform functionally to the Device Data Sheet
(DS30605C), except for the anomalies described
below.
None.
2003 Microchip Technology Inc.
DS80164A-page 1
PIC16C63A/65B/73B/74B
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS30605C), the following
clarifications and corrections should be noted.
Note 1:
When the SPI module is in Slave mode
pin
control
enabled
with
SS
(SSPCON<3:0> =
0100),
the SPI module
will reset if the SS pin is set to V
DD
.
2:
If the SPI is used in Slave mode with
CKE = '1', then SS pin control must be
enabled.
3: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100),
the state of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC, controls the
state that is read back from the
TRISC<5> bit (see Section 5.3 for infor-
mation on PORTC). If Read-Modify-
Write instructions, such as
BSF,
are
performed on the TRISC register while
the SS pin is high, this will cause the
TRISC<5> bit to be set, thus disabling
the SDO output.
1. Module: SSP (SPI
TM
Mode)
In Section 10.2 (“SPI Mode”), Figure 10-1 and the
note box immediately beneath it have been
amended to better demonstrate the Peripheral OE
line of the SSP module and describe its relation-
ship to the TRISC<5> bit of PORTC.
Changes are indicated in
bold.
FIGURE 10-1:
SSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
SSPBUF reg
Write
SSPSR reg
RC4/SDI/SDA
bit0
Shift
Clock
RC5/SDO
Peripheral OE
SS Control
Enable
RA5/SS/AN4
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
Edge
Select
RC3/SCK/SCL
TRISC<3>
Prescaler T
CY
4, 16, 64
DS80164A-page 2
2003 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2. Module: Packaging (Pinout and Product
Identification)
PIC16C63A and PIC16C73B devices are now
offered in 28-pin near chip-scale micro lead frame
packages (commonly known as “QFN”). This
packaging type has been added to the product line
since the latest revision of the Device Data Sheet.
The addition of this option requires the following
additions to the Device Data Sheet. The
referenced figures and tables follow this text.
1. The “Pin Diagram” on page 2 of the Data Sheet
is amended with the addition of the 28-pin QFN
pinout, shown in Figure 1.
2. Table 3-1 of Section 3.0 (“Architectural
Overview”) is replaced with an updated version
that adds a column for QFN pin assignments.
All new information is indicated in
bold.
3. Section 18.1 (“Package Marking Information”)
is amended to include a marking template and
example for 28-pin QFN devices. These are
shown in Figure 2.
4. Section 18.0 (“Package Information”) is
amended to include the mechanical drawings
of the 28-pin QFN package. These are shown
in Figure 3 and Figure 4, respectively.
5. Table B-1 (“Device Differences”) is amended to
include the 28-pin QFN for the PIC16C63A and
PIC16C73B devices.
FIGURE 1:
PINOUT DIAGRAM FOR PIC16C63A AND PIC16C73B, 28-PIN QFN
RA1/AN1
RA0/AN0
MCLR/V
PP
RB7
RB6
RB5
RB4
28 27 26 25 24 23 22
1
21
2
20
3
PIC16C63A
19
18
4
PIC16C73B
17
5
16
6
7
15
9 10 11 12 13 14
8
QFN (28-pin)
RA2/AN2
RA3/AN3/V
REF
+
RA4/T0CKI
RA5/AN4/SS
V
SS
OSC1/CLKI
OSC2/CLKO
RB3
RB2
RB1
RB0/INT
V
DD
V
SS
RC7/RX/DT
FIGURE 2:
PACKAGE MARKING TEMPLATE FOR PIC16C63A AND PIC16C73B, 28-PIN QFN
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
PIC16C63A
-I/ML
0310017
2003 Microchip Technology Inc.
DS80164A-page 3
PIC16C63A/65B/73B/74B
TABLE 3-1:
Pin Name
OSC1/CLKIN
OSC2/CLKOUT
PIC16C63A/73B PINOUT DESCRIPTION
DIP
Pin#
9
10
SOIC
Pin#
9
10
QFN
Pin#
6
7
I/O/P
Type
I
O
Buffer
Type
Description
ST/CMOS
(3)
Oscillator crystal input/external clock source input.
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
Master clear (RESET) input or programming voltage input.
This pin is an active low RESET to the device.
PORTA is a bidirectional I/O port.
RA0 can also be analog input 0
(4)
.
RA1 can also be analog input 1
(4)
.
RA2 can also be analog input 2
(4)
.
RA3 can also be analog input 3 or analog reference
voltage
(4)
.
RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5 can also be analog input 4
(4)
or the slave select for
the synchronous serial port.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
MCLR/V
PP
1
1
26
I/P
ST
RA0/AN0
(4)
RA1/AN1
(4)
RA2/AN2
(4)
RA3/AN3/V
REF
(4)
RA4/T0CKI
RA5/SS/AN4
(4)
2
3
4
5
6
7
2
3
4
5
6
7
27
28
1
2
3
4
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
TTL
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
V
SS
V
DD
Legend:
I = input
— = Not used
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
8, 19
20
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
8, 19
20
18
19
20
21
22
23
24
25
8
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
P
TTL/ST
(1)
TTL
TTL
TTL
TTL
TTL
TTL/ST
TTL/ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin.
Interrupt-on-change pin.
Interrupt-on-change pin. Serial programming clock.
Interrupt-on-change pin. Serial programming data.
PORTC is a bidirectional I/O port.
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3 can also be the synchronous serial clock input/output
for both SPI and I
2
C modes.
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I
2
C mode).
RC5 can also be the SPI Data Out (SPI mode).
RC6 can also be the USART Asynchronous Transmit
or Synchronous Clock.
RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
O = output
TTL = TTL input
I/O = input/output
P = power
ST = Schmitt Trigger input
Note 1:
2:
3:
4:
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
A/D module is not available in the PIC16C63A.
DS80164A-page 4
2003 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 3:
28-PIN QFN PACKAGE (DRAWING 1, PACKAGING)
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)
E
E1
EXPOSED
METAL
PADS
Q
D1
2
1
n
R
CH X 45°
E2
L
B
D
D2
p
TOP VIEW
α
BOTTOM VIEW
A2
A1
A3
A
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Base Thickness
Overall Width
Molded Package Width
Exposed Pad Width
Overall Length
Molded Package Length
Exposed Pad Length
Lead Width
Lead Length
Tie Bar Width
Tie Bar Length
Chamfer
Mold Draft Angle Top
Units
Dimension Limits
n
p
A
A2
A1
A3
E
E1
E2
D
D1
D2
B
L
R
Q
CH
α
MIN
.000
.140
.140
.009
.020
.005
.012
.009
INCHES
NOM
28
.026 BSC
.033
.026
.0004
.008 REF
.236 BSC
.226 BSC
.146
.236 BSC
.226 BSC
.146
.011
.024
.007
.016
.017
MAX
.039
.031
.002
.152
.152
.014
.030
.010
.026
.024
12°
MILLIMETERS*
MIN
NOM
28
0.65 BSC
0.85
0.65
0.00
0.01
0.20 REF
6.00 BSC
5.75 BSC
3.55
3.70
6.00 BSC
5.75 BSC
3.55
3.70
0.23
0.28
0.50
0.60
0.13
0.17
0.30
0.40
0.24
0.42
MAX
1.00
0.80
0.05
3.85
3.85
0.35
0.75
0.23
0.65
0.60
12°
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC equivalent: mMO-220
Drawing No. C04-114
2003 Microchip Technology Inc.
DS80164A-page 5
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