or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1009
Introduction_01.4
Introduction
LatticeXP2 Family Data Sheet
Introduction
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-
ture referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with
FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low
cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked
Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
Lattice Diamond
®
design software allows large and complex designs to be efficiently implemented using the
LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis
tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools
to place and route the design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and
back-annotates it into the design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By
using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2
LatticeXP2 Family Data Sheet
Architecture
June 2013
Data Sheet DS1009
Architecture Overview
Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sys-
DSP™ Digital Signal Processing blocks as shown in Figure 2-1.
On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks.
In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™
peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the con-
figuration SRAM. With this technology, expensive external configuration memory is not required, and designs are
secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via
wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many
applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory
Blocks at user request.
There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building
blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic
and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be imple-
mented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used
per row.
LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit
memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addi-
tion, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumu-
lators, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the
LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.
PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic
also includes pre-engineered support to aid in the implementation of high speed source synchronous standards
such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.
The LatticeXP2 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is
configured, the device enters into user mode with these registers SET/RESET according to the configuration set-
ting, allowing device entering to a known state for predictable system function.
Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four
General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.
The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates
and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a
sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided
between banks two and three.
This family also provides an on-chip oscillator. LatticeXP2 devices use 1.2V as their core voltage.
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Microsoft first proposed the concept of underwater data centers in 2014 , believing at the time that the concept had the potential to provide high-speed cloud services to coastal populations and save ...
uart1 needs to build its own peripherals.After configuring uart1 according to the datasheet, it still doesn't work.Later I found out that the uart0 on the board "corresponds" to the virtual serial por...
Dear experts: Q: Does WinCE contain the following components: Similar to the device manager in WinXP, I can check what devices the system has? Whether they are enabled, etc. etc........ Thanks...........
[hide]Due to the particularity of LED processing and manufacturing, the current and voltage characteristics of LEDs produced by different manufacturers or even by the same manufacturer in the same bat...
[i=s]This post was last edited by lonerzf on 2014-8-17 17:46[/i] In the previous design process, I encountered a situation where there was no suitable input power supply. At that time, there was only ...
S3C6410+3G module, running Linux, using udp to establish a connection with the server, sendto operates normally, data is sent successfully, and the return result is correct. The recvfrom operation fai...
On August 23rd, Geely's subsidiary, Jiyao Tongxing, announced it has the industry's largest advanced production capacity for tandao
batteries
, with eight production bases across China. Jiy...[Details]
When you are happily watching NBA or football, your wife asks you to turn off the lights in the bedroom. Would you be depressed? Of course, unless you are not afraid of your wife.
Now you are ...[Details]
As more and more consumers purchase new energy vehicles, the safety of electric vehicles has become a major concern. This has been particularly prominent following a series of electric vehicle fire...[Details]
"Have you set your calendar reminder?"
On August 24, Nvidia Robotics' official account posted a photo of a black gift box on a social media platform, with an attached greeting card sig...[Details]
Current Development Status of DVR Market
A DVR, or digital video recorder, uses a hard disk for recording, unlike traditional analog video recorders. It's often called a DVR because it's a com...[Details]
In mobile technology, sensors are the primary input for measured signals and form a component of a sensor system. They include sensitive and transducer elements connected to carriers and circuits. ...[Details]
Capable of providing precise and efficient thermal management for artificial intelligence computing power, intelligent sensing and autonomous driving systems
Shenzhen, ...[Details]
On August 25th, SK Hynix announced that it has completed development and entered mass production of its 321-layer, 2Tb QLC NAND flash memory product. This achievement marks the world's first applic...[Details]
On August 22nd, Lantu Motors unveiled a new technology called "Lanhai Intelligent Hybrid" during a live broadcast of CCTV News' "Top Laboratory." The name sounds like another new term, but a closer...[Details]
SMT placement machines are important equipment in surface mount technology (Surface Mount Technology). Their performance has a decisive impact on the quality and efficiency of electronic manufactur...[Details]
1. Multi-channel DAC technology bottleneck
Currently,
the development of multi-channel DAC technology focuses on two core challenges.
First, industrial applications urgently ...[Details]
A multilevel inverter converts a DC signal into a multilevel staircase waveform. Instead of a straight positive-negative output waveform, the output waveform of a multilevel inverter alternates in ...[Details]
Chinese characters are extensive and profound, and there are many different names for ESD tubes. How many of them do you know?
As far as I know, ESD diodes are currently known as ESD p...[Details]
Reflow soldering, as an electronics assembly process, has become a vital component of the electronics manufacturing industry. Choosing reflow soldering equipment is crucial for improving production...[Details]
Linear motor modules have become the "sweet spot" in various fields due to their advantages such as long stroke, fast speed, high precision, smooth operation and long life. Different models of line...[Details]
Talking
京公网安备 11010802033920号
EEWORLD
