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89H32NT24AG2ZBHL8

Description
pci interface IC pciE switch
Categorysemiconductor    Other integrated circuit (IC)   
File Size326KB,7 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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89H32NT24AG2ZBHL8 Overview

pci interface IC pciE switch

89H32NT24AG2ZBHL8 Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryPCI Interface IC
RoHSN
TypeSwitch - PCIe
Maximum Clock Frequency125 MHz
Number of Lanes32 Lane
Number of Ports24 P
Operating Supply Voltage1 V, 2.5 V, 3.3 V
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseFCBGA-484
Data Bus Width32/64 bi
Maximum Data Rate256 Gbps
Minimum Operating Temperature0 C
PackagingReel
Factory Pack Quantity600
VersiGen2
®
32-Lane 24-Port PCIe® Gen2
System Interconnect Switch with
Non-Transparent Bridging
89HPES32NT24AG2
Product Brief
Device Overview
The 89HPES32NT24AG2 is a member of the IDT family of PCI
Express® switching solutions. The PES32NT24AG2 is a 32-lane, 24-
port system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simulta-
neous peer-to-peer traffic flows. Target applications include multi-host or
intelligent I/O based systems where inter-domain communication is
required, such as servers, storage, communications, and embedded
systems.
With Non-Transparent Bridging functionality and innovative Switch
Partitioning feature, the PES32NT24AG2 allows true multi-host or multi-
processor communications in a single device. Integrated DMA control-
lers enable high-performance system design by off-loading data transfer
operations across memories from the processors. Each lane is capable
of 5 GT/s link speed in both directions and is fully compliant with PCI
Express Base Specification 2.1.
Features
High Performance Non-Blocking Switch Architecture
32-lane, 24-port PCIe switch with flexible port configuration
Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
Delivers up to 32 GBps (256 Gbps) of switching capacity
Supports 128 Bytes to 2 KB maximum payload size
Low latency cut-through architecture
Supports one virtual channel and eight traffic classes
Port Configurability
Four x8 stacks
Two x8 stacks, each configurable as:
• One x8 port
• Two x4 ports
• Four x2 ports
• Eight x1 ports
• Several combinations of the above lane widths
Two x4 stacks configurable as:
• One x8 port
• Two x4 ports
• Four x2 ports
• Several combinations of the above lane widths
Automatic per port link width negotiation
(x8
x4
x2
x1)
Crosslink support
Automatic lane reversal
Per lane SerDes configuration
De-emphasis
Receive equalization
Drive strength
Innovative Switch Partitioning Feature
Supports up to 8 fully independent switch partitions
Logically independent switches in the same device
Configurable downstream port device numbering
Supports dynamic reconfiguration of switch partitions
Dynamic port reconfiguration — downstream, upstream,
non-transparent bridge
Dynamic migration of ports between partitions
Movable upstream port within and between switch partitions
Non-Transparent Bridging (NTB) Support
Supports up to 8 NT endpoints per switch, each endpoint can
communicate with other switch partitions or external PCIe
domains or CPUs
6 BARs per NT Endpoint
Bar address translation
All BARs support 32/64-bit base and limit address translation
Two BARs (BAR2 and BAR4) support look-up table based
address translation
32 inbound and outbound doorbell registers
4 inbound and outbound message registers
Supports up to 64 masters
Unlimited number of outstanding transactions
Multicast
Compliant with the PCI-SIG multicast
Supports 64 multicast groups
Supports multicast across non-transparent port
Multicast overlay mechanism support
ECRC regeneration support
Integrated Direct Memory Access (DMA) Controllers
Supports up to 2 DMA upstream ports, each with 2 DMA chan-
nels
Supports 32-bit and 64-bit memory-to-memory transfers
Fly-by translation provides reduced latency and increased
performance over buffered approach
Supports arbitrary source and destination address alignment
Supports intra- as well as inter-partition data transfers using
the non-transparent endpoint
Supports DMA transfers to multicast groups
Linked list descriptor-based operation
Flexible addressing modes
Linear addressing
Constant addressing
Quality of Service (QoS)
Port arbitration
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 7
©
2009 Integrated Device Technology, Inc.
September 15, 2009

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