TSHS-101-D-32-H-SAD datasheet, PDF

TSHS-101-D-32-H-SAD: DescriptionBoard Connector, 2 Contact(s), 2 Row(s), Male, Straight, Black Insulator, Receptacle; CategoryThe connector The connector; File Size133KB，1 Pages; ManufacturerMajor League Electronics; Websitehttp://www.mlelectronics.com/

Download Datasheet Parametric View All

TSHS-101-D-32-H-SAD Overview

Board Connector, 2 Contact(s), 2 Row(s), Male, Straight, Black Insulator, Receptacle

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1163028039
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	MATING PIN LENGTH=1.130 INCH
Board mount options	EDGE MOUNT
body width	0.2 inch
subject depth	0.1 inch
body length	0.1 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	GOLD (30) OVER NICKEL (50)
Contact completed and terminated	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
contact mode	RECTANGULAR
Contact style	SQ PIN-SKT
Insulation resistance	5000000000 Ω
Insulator color	BLACK
insulator material	GLASS FILLED POLYESTER
JESD-609 code	e0
Manufacturer's serial number	TSHS
Match contact row spacing	0.1 inch
Installation method	STRAIGHT
Number of connectors	ONE
PCB row number	2
Number of rows loaded	2
Maximum operating temperature	125 °C
Minimum operating temperature	-65 °C
PCB contact pattern	RECTANGULAR
Plating thickness	30u inch
Rated current (signal)	3 A
Guideline	UL
reliability	COMMERCIAL
Total number of contacts	2

【Book Collection】EWB simulation experiment of digital electronic technology: ...; wzt Embedded System

Analog Circuit Follower Demonstration: Analog circuit follower demonstration http://www.kxflash.com/f/200882738.html...; fighting Analog electronics

ZTE 3G Module Selection Manual: Please check the attachment!Wish you all Happy New Year! Everything goes well! Good health! Happy family! Good work! Promotion! Lots of money!...; clever0725 RF/Wirelessly

Cainiao Consulting cpld: I saw that some pins of the FPGA's jtag interface need to be connected to pull-up resistors. Do the CPLD's jtag interface also need to be connected to pull-up resistors? I use EPM570......; zxdongyuan FPGA/CPLD

LPC-link2 external expansion board--PCB show: The PCB is smaller than expected. The plan was to place the interfaces on both sides. In the actual layout, it was found that the interfaces do not take up much space and can be placed on the right si...; le062 NXP MCU

[AN-777 Application Note] Dual-Channel AD9884A Design Guidelines for UXGA Solutions: Introduction: With the AD9884A, pixel clock rates in excess of 140 MHz can be achieved using a dual-chip "ping-pong" configuration....; EEWORLD社区 ADI Reference Circuit

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components