FQ245 · FQ235 · FQ225 · FQ215 · FQ205
FlexQ
TM
I
5 Volt Synchronous x18 First-In/First-Out Queue
Memory Configuration
4,096 x 18
2,048 x 18
1,024 x 18
512 x 18
256 x 18
Device
FQ245
FQ235
FQ225
FQ215
FQ205
Key Features:
•
•
•
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 100MHz)
Independent Write and Read cycle time
5V power supply
Reset clears all previously programmed configurations including Write and Read pointers.
Preset for Almost Full (
PRAF
) and Almost Empty (
PRAE
) offsets values
Parallel programming of
PRAF
and
PRAE
offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
Asynchronous output enable tri-state data output drivers
Available packages: 64 - pin Plastic Thin Quad Flat Package (TQFP), 64 - pin Slim Thin Quad Flat Package
(STQFP)
(0°C to 70°C) Commercial operating temperature available
(-40°C to 85°C) Industrial operating temperature available
Product Description:
HBA’s FlexQ™ I offers industry leading FIFO queuing bandwidth (up to 1.8 Gbps), with a wide range of memory configurations
(from 256 x 18 to 4,096 x 18). System designer has full flexibility of implementing deeper and wider queues with Write (
WEXI
and
WEXO
) and Read ( REXI and
REXO
) expansion features using Daisy Chain technique. Full, Empty, and Half Full
indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty
(Parallel) indicators allow implementation of virtual queue depths.
Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-
matching capability.
Data is written into the queue at the low to high transition of WCLK if
WEN
is asserted. Data is read from the queue at the low
to high transition of RCLK if
REN
is asserted.
Reset clears all previously programmed configurations by providing a low pulse on
RST
pin. In addition, Write and Read
pointers to the queue are initialized to zero.
These FlexQ™ I devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
5F118C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
Page 1 of 26
FQ245 · FQ235 · FQ225 · FQ215 · FQ205
FlexQ
TM
I
Block Diagram of Single Synchronous Queue
4,096 x 18 / 2 ,048 x 18 / 1,024 x 18 / 512 x 18 / 256 x 18
RESET (RST )
WRITE CLOCK (WCLK)
WRITE ENABLE ( WEN )
LOAD ( LOAD )
DATA IN (D
17 - 0
)
FULL FLAG ( FULL )
PROGRAMMABLE ( PRAE)
HALF - FULL FLAG ( HALF )
FQ245
FQ235
FQ225
FQ215
FQ205
READ CLOCK (RCLK)
READ ENABLE ( REN )
OUTPUT ENABLE (OE )
DATA OUT (Q
17 - 0
)
EMPTY FLAG ( EMPTY )
PROGRAMMABLE ( PRAF)
WEXO
REXO
FIRST LOAD (FIRST )
READ EXPANSION IN (
REXI
)
WRITE EXPANSION IN (
WEXI
)
Figure 1. Single Device Configuration Signal Flow Diagram
5F118C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
Page 2 of 26
FQ245 · FQ235 · FQ225 · FQ215 · FQ205
FlexQ
TM
I
WCLK
LOAD
WEN
Write Control
Logic
Offset Register
FULL
PRAF
Flag Logic
EMPTY
PRAE
( WEXO) / HALF
Write Pointer
D
17-0
x18
Input Register
SRAM
Output Register
Output
Buffer
Q
17-0
x18
OE
FIRST
Read Pointer
WEXI
(HALF) / WEXO
REXI
REXO
RCLK
REN
RST
Expansion Logic
Read Control
Logic
Reset
Figure 2. Device Architecture
5F118C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
Page 3 of 26
FQ245 · FQ235 · FQ225 · FQ215 · FQ205
FlexQ
TM
I
RCLK
LOAD
EMPTY
GND
REN
RST
D16
GND
D17
Q16
GND
Q17
Q15
50
PIN 1
64
63
62
61
60
59
58
57
56
Vcc
OE
55
54
53
52
51
49
Vcc
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
2
48
47
46
Q14
Q13
GND
Q12
Q11
Vcc
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
Vcc
3
4
5
43
6
7
8
40
9
39
10
38
11
37
12
13
14
15
16
17
18
19
22
23
24
25
26
28
29
30
31
20
21
27
32
Q3
35
34
33
36
42
41
45
44
WEXO/HALF
FIRST
WCLK
PRAE
PRAF
FULL
Q1
REXO
WEXI
REXI
WEN
Vcc
Q0
TQFP – 64 (Drw No: PF-01A; Order Code: PF)
STQFP – 64 (Drw No: TF-01A; Order Code: TF)
Top View
Figure 3. Device Pin Out
GND
Q2
5F118C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
Page 4 of 26
FQ245 · FQ235 · FQ225 · FQ215 · FQ205
FlexQ
TM
I
Pin #
Pin Name
Pin Symbol
Input/Output
Description
Reset is required to initialize Write and Read pointers
to the first position of the queue by setting
RST
low.
FULL
and PRAF will go high; EMPTY and
PRAE will go low. All data outputs will go low.
Previous programmed configurations will not be
maintained.
Writes data into queue during low to high transitions
of WCLK if
WEN
is set low.
Controls write operation into queue or offset registers
during low to high transition of WCLK.
LOAD
controls write/read, to/from offset registers
during low to high transition of WCLK/RCLK
respectively. Use in conjunction with
WEN
/
REN
.
57
Reset
RST
Input
19
20
Write Clock
Write Enable
Load Enable
WCLK
WEN
Input
Input
Input
59
LOAD
18
First Load
FIRST
Input
In single device configuration,
FIRST
is set low.
In depth expansion configuration,
FIRST
is set low
for the first device and set high for other devices in
the Daisy Chain.
21
Write Expansion
In
WEXI
Input
In single device configuration, WEXI is set low.
In depth expansion configuration, WEXI is
connected to WEXO of previous device in the Daisy
Chain.
18 - bit wide input data bus.
Reads data from queue during low to high transitions
of RCLK if
REN
is set low.
Controls read operation from queue or offset registers
during low to high transition of RCLK.
In single device configuration, REXI is set low.
In depth expansion configuration, REXI is connected
to
REXO
of previous device in the Daisy Chain.
Setting
OE
low activates the data output drivers.
Setting
OE
high deactivates the data output drivers
(High-Z).
18 - bit wide output data bus.
In depth expansion configuration,
REXO
is
connected to REXI of next device in the Daisy
Chain.
Queue is full when
FULL
goes low during the low to
high transition of WCLK. This prohibits further
writes into the queue.
63, 64, 1, 2, 3, 4,
5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15,
16
61
60
Data Inputs
D
17-0
Input
Read Clock
Read Enable
Read Expansion
In
RCLK
REN
Input
Input
24
REXI
Input
58
53, 52, 50, 48, 47,
45, 44, 42, 41, 39,
38, 37, 36, 34, 32,
31, 29, 28
27
Output Enable
OE
Input
Data Outputs
Q
17-0
Output
Read Expansion
Out
REXO
Output
25
Full Flag
FULL
Output
Table 1. Pin Descriptions
5F118C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
Page 5 of 26
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