PI6C485311
3.3V Low Skew 1-to-2
Differential to LVPECL Fanout Buffer
Features
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Pin-to-pin compatible to ICS85311
Maximum operation frequency: 800MHz
2 pair of differential LVPECL outputs
CLK,
n
CLK pair accepts LVDS, LVPECL, LVHSTL,
SSTL and HCSL input level
Output Skew: 100ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2ns (maximum)
3.3V power supply
Operating Temperature: -40
o
C to 85
o
C
Packaging (Pb-free & Green avaliable):
-
8-pin SOIC (W)
Description
The PI6C485311 is a high-performance low-skew LVPECL fanout
buffer. PI6C485311 features two selectable differential inputs and
translates to four LVPECL ultra-low jitter outputs. The inputs
can also be configured to single-ended with external resistor bias
circuit. The CLK input accepts LPECL or LVDS or LVHSTL or
SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL
or CML signals. PI6C485311 is ideal for differential to LVPECL
translations and/or LVPECL clock distribution. Typical clock
translation and distribution applications are data-communications
and telecommunications.
Block Diagram
Q
0
n
Q
0
Q
1
n
Q
1
Pin Diagram
1
2
3
4
Q0
nQ0
Q1
nQ1
8
7
6
5
V
CC
CLK
nCLK
V
EE
CLK
n
CLK
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PS8865D
11/14/06
PI6C485311
3.3V Low Skew 1-to-2
Differential to LVPECL Fanout Buffer
Pin Description
Name
V
EE
CLK
n
CLK
Pin #
5
7
6
8
3.4
1,2
Type
P
I_PD
I_PU
P
O
O
Connect to Negative power supply
Non-inverting differential clock input
Inverting differential clock input
Connect to 3.3V.
Description
V
CC
Q
1
,
n
Q
1
Q
0
,
n
Q
0
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Note:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol
C
IN
R_pullup
R_pulldown
Parameter
Input Capacitance
Input Pullup Resistance
Input Pulldown Resistance
50
50
Conditions
Min.
Typ.
Max.
4
Units
pF
KΩ
Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
T
STG
Parameter
Supply voltage
Input voltage
Output voltage
Storage temperature
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
Min.
Typ.
Max.
4.6
V
CC
+0.5V
V
CC
+0.5V
150
o
C
Units
V
Note:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fi
cations only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
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P8865D
11/14/06
PI6C485311
3.3V Low Skew 1-to-2
Differential to LVPECL Fanout Buffer
Operating Conditions
Symbol
V
CC
T
A
I
EE
Parameter
Power Supply Voltage
Ambient Temperature
Power Supply Current
500 MHz
Conditions
Min.
3.0
-40
Typ.
3.3
Max.
3.6
85
60
Units
V
o
C
mA
Differential DC Input Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.0V to 3.6V unless otherwise stated.)
Symbol
I
IH
I
IL
V
PP
V
CMR
Input High
Current
Input Low
Current
Parameter
n
CLK
Conditions
V
IN
= V
CC
= 3.6V
V
IN
= V
CC
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
Min.
Typ.
Max.
5
150
Units
uA
uA
uA
uA
CLK
n
CLK
-150
-5
0.15
V
EE
+0.5
1.3
V
CC
-
0.85V
CLK
Peak-to-peak Voltage
Common Mode Input Voltage
(1, 2)
V
V
Notes:
1. For single ended applications, the maximum input voltage for CLK and nCLK is V
CC
+0.3V
2. Common mode voltage is defined as V
IH
.
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P8865D
11/14/06
PI6C485311
3.3V Low Skew 1-to-2
Differential to LVPECL Fanout Buffer
LVPECL DC Characteristics
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Input High
Current
Input Low
Current
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.0V to 3.6V, R
L
= 50Ω to V
CC
- 2V, unless otherwise stated below.)
Parameter
n
CLK
Conditions
V
IN
= V
CC
= 3.6V
V
IN
= V
CC
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
Min.
Typ.
Max.
5
150
Units
CLK
n
CLK
-150
-5
0.3
V
EE
+1.5
V
CC
-1.4
V
CC
-2.0
0.6
1
V
CC
V
CC
-0.9
V
CC
-1.6
1.0
μA
CLK
Peak-to-peak Voltage
Common Mode Input Voltage; Note
(1,2)
Output High Voltage
Output Low Voltage
Peak-to-peak Output Voltage Swing
V
Notes:
1. For single ended applications, the maximum input voltage for PCLK and
n
PCLK is V
CC
+0.3V.
2. Common mode voltage is defined as V
IH
.
AC Characteristics
(1)
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.0V to 3.6V,
R
L
= 50Ω to V
CC
- 2V, unless otherwise stated below.
)
Symbol
f
max
t
Pd
Tsk(o)
Tsk(pp)
t
r
/t
f
odc
Parameter
Output Frequency
Propagation Delay
(2)
Output-to-output Skew
(3)
Part-to-part Skew
(4)
Output Rise/Fall time
Output duty cycle
20% - 80%
75
40
1.0
Conditions
Min.
Typ.
Max.
800
2.0
100
150
300
60
%
ps
Units
MHz
ns
Notes:
1. All parameters are measured at 500MHz unless noted otherwise
2. Measured from the V
CC
/2 of the input to the differential output crossing point
3
Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing
point.
4. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the
outputs differential crossing point.
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P8865D
11/14/06
PI6C485311
3.3V Low Skew 1-to-2
Differential to LVPECL Fanout Buffer
Applications Information
Wiring the differenctial input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
V
DD
Single Ended
Clock Input
R1
1K
CLK1
nCLK1
C1
0.1μ
R2
1K
Figure 2: Single-ended Signal Driving Differential Input
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P8865D
11/14/06
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