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Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
9/6/2013
1
IS43/46DR16160B
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row). The
address bits registered coincident with the Read or Write command are used to select the starting column location
(A0-A8) for the burst access and to determine if the auto precharge A10 command is to be issued. Prior to normal
operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
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