FIN1531 5V LVDS 4-Bit High Speed Differential Driver
August 2001
Revised August 2001
FIN1531
5V LVDS 4-Bit High Speed Differential Driver
General Description
This quad driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates 5V TTL/CMOS signal levels to
LVDS levels with a typical differential output swing of 350
mV which provides low EMI at ultra low power dissipation
even at high frequencies. This device is ideal for high
speed transfer of clock and data.
The FIN1531 can be paired with its companion receiver,
the FIN1532, or with any other Fairchild LVDS receiver.
Features
s
Greater than 400Mbs data rate
s
5V power supply operation
s
400ps max differential pulse skew
s
2.0ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Pin compatible with equivalent RS-422 and
PECL devices
s
16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
FIN1531M
FIN1531MTC
Package Number
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Input
EN
H
H
H
X
X
X
L
H
=
HIGH Logic Level
X
=
Don’t Care
Connection Diagram
Outputs
D
IN
H
L
OPEN
H
L
OPEN
X
D
OUT+
H
L
L
H
L
L
Z
D
OUT−
L
H
H
L
H
H
Z
EN
X
X
X
L
L
L
H
L
=
LOW Logic Level
Z
=
High Impedance
Pin Descriptions
Pin Name
D
IN1
, D
IN2
, D
IN3
, D
IN4
Description
5V TTL/CMOS Data Input
D
OUT1+
, D
OUT2
+
, D
OUT3+
, D
OUT4+
Non-inverting LVDS Output
D
OUT1−
, D
OUT2−
, D
OUT3−
, D
OUT4−
Inverting LVDS Output
EN
EN
V
CC
GND
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
© 2001 Fairchild Semiconductor Corporation
DS500505
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FIN1531
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Driver Short Circuit Current (I
OSD
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
−
0.5V to
+
6V
−
0.5V to
+
6V
−
0.5V to
+
6V
Continuous
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Operating Temperature (T
A
)
4.5V to 5.5V
0 to V
CC
−
40
°
C to
+
85
°
C
−
65
°
C to
+
150
°
C
150
°
C
≥
8000V
≥
400V
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
I
OFF
I
OS
V
IH
V
IL
I
IN
I
I(OFF)
I
OZ
V
IK
I
CC
Parameter
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Power Off Output Current
Short Circuit Output Current
Input HIGH Voltage
Input LOW Voltage
Input Current
Power-OFF Input Current
Disabled Output Leakage Current
Input Clamp Voltage
Power Supply Current
V
IN
=
0V or V
CC
V
CC
=
0V, V
IN
=
5.5V
EN
=
0.8V, EN
=
2.0V,
V
OUT
=
0V or 7V
I
IK
= −18
mA
No Load, V
IN
=
0V or V
CC
, Driver Enabled
R
L
=
100Ω, Driver Disabled
R
L
=
100Ω, V
IN
=
0V or V
CC
, Driver Enabled
C
IN
C
OUT
Input Capacitance
Output Capacitance
−1.5
−0.8
3.3
3.4
18
7
4.5
6
6
26
pF
pF
mA
V
CC
=
0V, V
OUT
=
5.5V
V
OUT
=
0V, Driver Enabled
V
OD
=
0V, Driver Enabled
2.0
GND
RL
=
100Ω, driver enabled,
See Figure 1
1.125
1.25
Test Conditions
Min
250
Typ
(Note 2)
350
450
25
1.375
25
50
−6
±6
V
CC
0.8
±20
50
±20
Max
Units
mV
mV
V
mV
µA
mA
V
V
µA
µA
µA
V
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
5.0V.
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2
FIN1531
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
t
ZHD
t
ZLD
t
HZD
t
LZD
Parameter
Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency(Note 6)
LVTTL Output Enable Time from Z to HIGH R
L
=
100Ω, C
L
=
10 pF,
LVTTL Output Enable Time from Z to LOW See Figure 4 and Figure 5 (Note 7)
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
200
250
5.0
5.0
5.0
5.0
R
L
=
100
Ω,
C
L
=
10 pF,
Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3 (Note 7)
Test Conditions
Min
Typ
(Note 3)
0.5
0.5
0.6
0.6
1.4
1.4
0.8
0.8
2.0
2.0
1.2
1.2
0.4
0.3
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
5V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
=
t
F
<
1 ns, 0V to 3V, 50% Duty Cycle; Output V
OD
>
250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Note 7:
Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
3
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FIN1531
FIGURE 1. Differential Driver DC Test Circuit
Note A:
Input pulses have frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note B:
C
L
includes all probe and jig capacitances
FIGURE 2. Differential Driver Propagation Delay and
Transition Time Test Circuit
Note A:
Input pulses have the following characteristics:
Frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note B:
C
L
includes probes and jig capacitance
FIGURE 3. AC Waveforms
FIGURE 4. Differential Driver Enable and
Disable Test Circuit
FIGURE 5. Enable and Disable AC Waveforms
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FIN1531
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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