MR0A08B
FEATURES
•
•
•
•
•
•
•
•
•
3.3 Volt power supply
Fast 35 ns read/write cycle
SRAM compatible timing
Native non-volatility
Unlimited read & write endurance
Data always non-volatile for >20 years at temperature
Commercial and industrial temperatures
All products meet MSL-3 moisture sensitivity level
RoHS-Compliant TSOP2 and BGA packages
128K x 8 MRAM
48-ball FBGA
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and
MRAM in system for simpler, more efficient design
• Improves reliability by replacing battery-backed
SRAM
INTRODUCTION
44-pin TSOP2
The
MR0A08B
is a 1,048,576-bit magnetoresistive random access
memory (MRAM) device organized as 131,072 words of 8 bits. The
MR0A08B offers SRAM compatible 35 ns read/write timing with unlim-
ited endurance.
Data is always non-volatile for greater than 20-years. Data is automatically protected on
power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
The MR0A08B is the ideal memory solution for applications that must permanently store and
retrieve critical data and programs quickly.
The
MR0A08B
is available in small footprint 400-mil, 44-lead plastic small-outline TSOP
type-2 package, 8 mm x 8 mm, or a 48-pin ball grid array (BGA) package with 0.75 mm ball
centers. (The 32-SOIC package options is obsolete and no longer available for new orders.)
These packages are compatible with similar low-power SRAM products and other non-vola-
tile RAM products.
The
MR0A08B
provides highly reliable data storage over a wide range of temperatures. The
product is offered with commercial temperature range (0 to +70 °C) and industrial tempera-
ture range (-40 to +85 °C).
RoHS
Copyright © 2018 Everspin Technologies
1
MR0A08B Rev. 8.6, 3/2018
MR0A08B
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
BENEFITS...............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS .......................................................................................4
Figure 1 – MR0A08B Block Diagram ...................................................................................................................... 4
Table 1 – Pin Functions ............................................................................................................................................... 4
Figure 2 – Pin Diagrams for Available Packages (Top View) 1 ...................................................................... 5
OPERATING MODES .............................................................................................................................5
Table 2 – Operating Modes ....................................................................................................................................... 5
ELECTRICAL SPECIFICATIONS ............................................................................................................6
Table 3 – Absolute Maximum Ratings................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Table 4 – Operating Conditions............................................................................................................................... 7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Diagram ............................................................................................... 8
DC CHARACTERISTICS .........................................................................................................................9
Table 5 – DC Characteristics...................................................................................................................................... 9
Table 6 – Power Supply Characteristics ................................................................................................................ 9
TIMING SPECIFICATIONS ................................................................................................................. 10
Table 7 – Capacitance ...............................................................................................................................................10
Table 8 – AC Measurement Conditions ..............................................................................................................10
Figure 4 – Output Load Test Low and High .......................................................................................................10
Figure 5 – Output Load Test All Others ...............................................................................................................10
Copyright © 2018 Everspin Technologies
2
MR0A08B Rev. 8.6, 3/2018
MR0A08B
TABLE OF CONTENTS (CONT’D)
Read Mode .................................................................................................................................... 11
Table 9 – Read Cycle Timing ...................................................................................................................................11
Figure 6 – Read Cycle 1 .............................................................................................................................................12
Figure 7 – Read Cycle 2 .............................................................................................................................................12
Write Mode.................................................................................................................................... 13
Table 10 – Write Cycle Timing 1 (
W
Controlled ).............................................................................................13
Figure 8 – Write Cycle Timing 1 (W Controlled) ...............................................................................................14
Table 11 – Write Cycle Timing 2 (
E
Controlled) ................................................................................................15
Figure 9 – Write Cycle Timing 2 (
E
Controlled) ................................................................................................16
Table 12 – Write Cycle Timing 3 (Shortened t
WHAX
,
W
and
E
Controlled) .............................................17
Figure 10 – Write Cycle Timing 3 (Shortened t
WHAX
,
W
and
E
Controlled) ...........................................17
ORDERING INFORMATION ............................................................................................................... 18
Table 13 – Ordering Part Number System for Parallel I/O MRAM..............................................................18
Table 14 – MR0A08B Ordering Part Numbers 1 ...............................................................................................18
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 19
Figure 11 – 44-TSOP2 Package Outline...............................................................................................................19
Figure 12 – 48-BGA Package Outline ...................................................................................................................20
Figure 13 – 32-SOIC Package Outline 1 ..............................................................................................................21
REVISION HISTORY ........................................................................................................................... 22
HOW TO CONTACT US ....................................................................................................................... 23
Copyright © 2018 Everspin Technologies
3
MR0A08B Rev. 8.6, 3/2018
MR0A08B
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – MR0A08B Block Diagram
G
OUTPUT
ENABLE
BUFFER
7
10
ROW
DECODER
COLUMN
DECODER
OUTPUT ENABLE
A[16:0]
17
ADDRESS
BUFFER
E
CHIP
ENABLE
BUFFER
8
128k x 8
BIT
MEMORY
ARRAY
8
SENSE
AMPS
8
OUTPUT
BUFFER
8
W
WRITE
ENABLE
BUFFER
FINAL
WRITE
DRIVERS
8
WRITE
DRIVER
8
DQ[7:0]
WRITE ENABLE
Table 1 – Pin Functions
Signal Name
A
E
W
G
DQ
V
DD
V
SS
DC
NC
Function
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection -
Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6
(BGA); Pin 30 (SOIC) Reserved For Future Expansion
Copyright © 2018 Everspin Technologies
4
MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 2 – Pin Diagrams for Available Packages (Top View) 1
DC
NC
A
A
A
A
A
E
DQ0
DQ1
V
DD
V
SS
DQ2
DQ3
W
A
A
A
A
A
DC
DC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC
NC
DC
NC
NC
A
A
G
DQ7
DQ6
V
SS
V
DD
DQ5
DQ4
DC
A
A
A
A
A
DC
DC
DC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A
15
NC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
1
DC
NC
DQ
0
2
G
DC
NC
DQ
1
DQ
2
3
A
0
A
3
A
5
NC
DC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
E
NC
DQ
5
DQ
6
6
DC
DC
DQ
4
A
B
C
D
E
F
G
H
V
SS
V
DD
DQ
3
V
DD
V
SS
DQ
7
NC
NC
A
8
NC
W
A
11
NC
NC
NC
NC
44 Pin TSOP2
Note:
32 Pin SOIC 1
48 Pin FBGA
1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer
available for new orders.
OPERATING MODES
Table 2 – Operating Modes
E
1
H
L
L
L
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
5
G
1
X
H
L
X
W
1
X
H
H
L
Mode
Not selected
Output disabled
Byte Read
Byte Write
V
DD
Current
I
SB1
, I
SB2
I
DDR
I
DDR
I
DDW
DQ[7:0] 2
Hi-Z
Hi-Z
D
Out
D
in
Copyright © 2018 Everspin Technologies
MR0A08B Rev. 8.6, 3/2018
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