Intel® 7500/7510/7512 Scalable Memory
Buffer
Datasheet
April 2011
Document Number: 322824-002
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Intel® 7500/7510/7512 Scalable Memory Buffer Datasheet
Contents
1
Introduction
.............................................................................................................. 7
1.1
Intel
®
7500/7510/7512 Scalable Memory Buffer Overview........................................ 7
1.2
Intel
®
7500/7510/7512 Scalable Memory Buffer Functionality ................................... 7
1.2.1
Intel
®
SMI Functionality .......................................................................... 7
1.2.2
DDR3 Functionality ................................................................................. 7
1.2.3
Management/DFx Functionality................................................................. 9
1.3
Intel 7500/7510/7512 Scalable Memory Buffer Interfaces and Logical View ................. 9
1.3.1
Intel SMI Channel Interface ................................................................... 10
1.3.2
DDR3 Bus Interface .............................................................................. 11
1.3.3
SMBus Slave Interface .......................................................................... 11
1.3.4
JTAG Interface ..................................................................................... 12
1.4
Debug and Logic Analyzer Interface ..................................................................... 12
1.5
References ....................................................................................................... 12
1.6
List of Terms and Abbreviations .......................................................................... 13
Electrical and Power
................................................................................................ 15
2.1
Storage Conditions ............................................................................................ 15
2.2
Electrical DC Parameters .................................................................................... 15
2.2.1
Absolute Maximum Ratings .................................................................... 15
2.2.2
Component Operating Parameters .......................................................... 16
2.2.3
Scalable Memory Buffer Pin Power Supply Specifications ............................ 17
2.3
Reference Clock ................................................................................................ 18
2.3.1
Supported Clock Frequencies and Ratios .................................................. 18
2.4
DDR3 Signaling Specifications ............................................................................. 18
2.4.1
DC and AC Characteristics ..................................................................... 18
2.5
SMBus, TAP, and other CMOS I/O........................................................................ 21
2.6
VCCPWRGOOD and VDDPWRGOOD...................................................................... 23
2.7
RESET ............................................................................................................. 24
2.8
Intel 7500/7510/7512 Scalable Memory Buffer Overshoot/Undershoot Specifications.. 24
Signal Lists
.............................................................................................................. 27
3.1
Conventions ..................................................................................................... 27
3.2
Intel 7500/7510/7512 Scalable Memory Buffer Component Pin Description List.......... 28
Ballout and Package
................................................................................................ 31
4.1
Ballout Overview ............................................................................................... 31
4.2
Intel 7500/7510 Scalable Memory Buffer Pin Assignments
(Non-split Rail Implementation) ......................................................................... 31
4.3
Package information .......................................................................................... 38
4.4
Intel 7512 Scalable Memory Buffer Split Rail Implementation (Low Power SKU) ......... 40
Intel
®
7500/7510/7512 Scalable Memory Buffer Interfaces..................................... 10
SMBus Timing Waveform.................................................................................... 23
SMBus Valid Delay Timing Waveform ................................................................... 23
Overshoot and Undershoot Durations ................................................................... 25
Package Information.......................................................................................... 39
2
3
4
Figures
1-1
2-1
2-2
2-3
4-1
Tables
1-1
1-2
1-3
2DPC Supported Configurations............................................................................. 8
Intel
®
Scalable Memory Interconnect (Intel
®
SMI) Architecture
and Protocol Support on Intel
®
7500/7510/7512 Scalable Memory Buffer ................... 9
References ....................................................................................................... 12
Intel® 7500/7510/7512 Scalable Memory Buffer Datasheet
3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
3-1
3-2
4-1
4-2
4-3
4-4
Storage Condition Ratings...................................................................................15
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(See Note 1) .....................................................................................................15
Intel
®
7500 Scalable Memory Buffer Operating DC Electrical Parameters...................16
Intel
®
7510 Scalable Memory Buffer Operating Parameters (Standard SKU) ..............16
Intel
®
7512 Scalable Memory Buffer Operating Parameters (Low Power SKU) ............16
Intel 7500 Scalable Memory Buffer Active Power
Specifications at DDR3-1067 MT/s for a Single 1.1 V VR..........................................17
Intel 7510 Scalable Memory Buffer Power Specifications at 1067
for a Single 1.11 V VR (Standard SKU) .................................................................17
Intel 7512 Scalable Memory Buffer Active Power Specifications at 1067 for
Two 1.1V VRs (a.k.a. Split-rail Implementation, Low Power SKU) .............................18
Intel 7500/7510/7512 Scalable Memory Buffer Clock Ratios ....................................18
DDR3 and DDR3L Signal Group DC Specifications...................................................18
DDR3 Electrical Characteristics and AC Timings at 800 MHz,
(VDDQ = 1.5 V ± 0.075 V) .................................................................................19
DDR3 Electrical Characteristics and AC Timings at 1066 MHz ...................................20
Recommended Operating Conditions for SMBUS, TAP, and other CMOS I/O Pins.........22
SMBus Signal Group AC Timing Specifications........................................................22
VCCPWRGOOD and VDDPWRGOOD AC and DC Characteristics .................................23
Recommended Operating Conditions for RST_N .....................................................24
Intel 7500/7510/7512 Scalable Memory Buffer Overshoot/Undershoot Specifications ..25
Signal Naming Conventions.................................................................................27
Pin Description ..................................................................................................28
Intel 7500/7510 Scalable Memory Buffer Ball Assignments - Left .............................31
Intel 7500/7510 Scalable Memory Buffer Ball Assignment - Middle ...........................32
Intel 7500/7510 Scalable Memory Buffer Ball Assignment - Right .............................32
Intel 7500/7510/7512 Scalable Memory Buffer Signals by Ball Number .....................33
4
Intel® 7500/7510/7512 Scalable Memory Buffer Datasheet
Revision History
Document
Number
322824
322824
Revision
Number
001
002
•
•
Description
Initial release of the document.
Added Intel 7510/7512 Scalable Memory Buffer
Date
March 2010
April 2011
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Intel® 7500/7510/7512 Scalable Memory Buffer Datasheet
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