74LCX38MX datasheet, PDF - EEWORLD Datasheet

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74LCX38MX: Descriptionlogic gates Qd 2-input nand gate; Categorylogic logic; File Size127KB，8 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74LCX38MX Overview

logic gates Qd 2-input nand gate

74LCX38MX Parametric

Parameter Name	Attribute value
Brand Name	Fairchild Semiconduc
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	SOIC
package instruction	SOP, SOP14,.25
Contacts	14
Manufacturer packaging code	14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY
Reach Compliance Code	compli
ECCN code	EAR99
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G14
JESD-609 code	e3
length	8.6235 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-DRAIN
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
propagation delay (tpd)	6.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.753 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
Base Number Matches	1

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74LCX38 Low Voltage Quad 2-Input NAND Gate (Open Drain) with 5V Tolerant Inputs

October 1995

Revised February 2005

74LCX38

Low Voltage Quad 2-Input NAND Gate (Open Drain)

with 5V Tolerant Inputs

General Description

The LCX38 contains four 2-input open drain NAND gates.

The inputs tolerate voltages up to 7V allowing the interface

of 5V systems to 3V systems.

The 74LCX38 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

5V tolerant inputs

2.3V to 3.6V V

specifications provided

5.0 ns t

max (V

3.3V), 10

A I

max

3.0V)

Power down high impedance inputs and outputs

24 mA output drive (V

Implements proprietary noise/EMI reduction circuitry

Latch-up performance exceeds 500 mA

ESD performance:

Human body model

2000V

Machine model

150V

Ordering Code:

Order Number

74LCX38M

74LCX38MX_NL

(Note 1)

74LCX38SJ

74LCX38MTC

74LCX38MTCX_NL

(Note 1)

Package

Number

M14A

M14D

MTC14

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1:

“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Pin Names

, B

DS012574

Description

Inputs

Outputs

www.fairchildsemi.com

74LCX38MX Related Products

	74LCX38MX	74LCX38SJX
Description	logic gates Qd 2-input nand gate	logic gates Qd 2-input nand gate
Brand Name	Fairchild Semiconduc	Fairchild Semiconductor
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	Fairchild	Fairchild
Parts packaging code	SOIC	SOP
package instruction	SOP, SOP14,.25	SOP, SOP14,.3
Contacts	14	14
Manufacturer packaging code	14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY	14LD,SOP,EIAJ TYPE II, 5.3MM WIDE
Reach Compliance Code	compli	compliant
ECCN code	EAR99	EAR99
series	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e3	e3
length	8.6235 mm	10.2 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	NAND GATE	NAND GATE
MaximumI(ol)	0.024 A	0.024 A
Humidity sensitivity level	1	1
Number of functions	4	4
Number of entries	2	2
Number of terminals	14	14
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	OPEN-DRAIN	OPEN-DRAIN
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Encapsulate equivalent code	SOP14,.25	SOP14,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
propagation delay (tpd)	6.5 ns	6.5 ns
Certification status	Not Qualified	Not Qualified
Schmitt trigger	NO	NO
Maximum seat height	1.753 mm	2.1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	3.9 mm	5.3 mm
Base Number Matches	1	1

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