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U404NL

Description
Small Signal Field-Effect Transistor, N-Channel, Junction FET
CategoryDiscrete semiconductor    The transistor   
File Size82KB,6 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Download Datasheet Parametric View All

U404NL Overview

Small Signal Field-Effect Transistor, N-Channel, Junction FET

U404NL Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid104555161
package instruction,
Reach Compliance Codeunknown
ECCN codeEAR99
FET technologyJUNCTION
JESD-609 codee0
Maximum operating temperature150 °C
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)0.5 W
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
SST/U401NL Series
New Product
Vishay Siliconix
Monolithic N-Channel JFET Duals
SST404NL
SST406NL
PRODUCT SUMMARY
Part Number
U401NL
SST/U404NL
SST/U406NL
U401NL
U404NL
U406NL
V
GS(off)
(V)
-0.5 to -2.5
-0.5 to -2.5
-0.5 to -2.5
V
(BR)GSS
Min (V)
-40
-40
-40
g
fs
Min (mS)
1
1
1
I
G
Typ (pA)
-2
-2
-2
jV
GS1
- V
GS2
j
Max (mV)
5
15
40
FEATURES
D
D
D
D
D
D
D
Anti Latchup Capability
Monolithic Design
High Slew Rate
Low Offset/Drift Voltage
Low Gate Leakage: 2 pA
Low Noise
High CMRR: 102 dB
BENEFITS
D
D
D
D
D
D
D
External Substrate Bias—Avoids Latchup
Tight Differential Match vs. Current
Improved Op Amp Speed, Settling Time Accuracy
Minimum Input Error/Trimming Requirement
Insignificant Signal Loss/Error Voltage
High System Sensitivity
Minimum Error with Large Input Signal
APPLICATIONS
D
Wideband Differential Amps
D
High-Speed,Temp-Compensated,
Single-Ended Input Amps
D
High-Speed Comparators
D
Impedance Converters
DESCRIPTION
The SST/U401NL series of high-performance monolithic dual
JFETs features extremely low noise, tight offset voltage and
low drift over temperature specifications, and is targeted for
use in a wide range of precision instrumentation applications.
This series has a wide selection of offset and drift
specifications with the U401NL featuring a 5-mV offset and
10-mV/_C drift.
Pins 4 and 8 of the SST series, and pin 4 of the U series part
numbers enable the substrate to be connected to a positive
polarity, external bias (V
DD
) to avoid latchup.
The U series, hermetically sealed TO-78 package is
available with full military processing. The SST series SO-8
package provides ease of manufacturing, and the
symmetrical pinout prevents improper orientation. The SO-8
package is available with tape-and-reel options for
compatibility with automatic assembly methods.
TO-78
Narrow Body SOIC
S
1
D
1
G
1
SUBSTRATE
1
2
3
4
8
7
6
5
SUBSTRATE
G
2
D
2
S
2
D
1
S
1
1
2
3
G
1
4
5
7
6
G
2
D
2
S
2
CASE, SUBSTRATE
Top View
Marking Codes:
SST404NL - 404NL
SST406NL - 406NL
Top View
U401NL
U404NL
U406NL
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Lead Temperature (
1
/
16
” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C
U Prefix . . . . . . . . . . . . . . . . . . . . . -65 to 200_C
SST Prefix . . . . . . . . . . . . . . . . . . . -55 to 150_C
For applications information see AN106.
Document Number: 72055
S-22448—Rev. A, 17-Feb-03
Storage Temperature :
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C
Power Dissipation :
Per Side
a
. . . . . . . . . . . . . . . . . . . . . . . . 300 mW
Total
b
. . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
www.vishay.com
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