DATASHEET
EEPROM PROGRAMMABLE CLOCK GENERATOR
Description
The IDT5V49EE503 is a programmable clock generator
intended for high performance data-communications,
telecommunications, consumer, and networking
applications. There are four internal PLLs, each individually
programmable, allowing for four unique non-integer-related
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from one of
the two redundant clock inputs. Automatic or manual
switchover function allows any one of the redundant clocks
to be selected during normal operation.
The IDT5V49EE503 is in-system, programmable and can
be programmed through the use of I
2
C interface. An
internal EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
Each of the four PLLs has an 7-bit reference divider and a
12-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation
and/or fractional divides are allowed on two of the PLLs.
There are a total of four 8-bit output dividers. The outputs
are connected to the PLLs via a switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function is programmable.
IDT5V49EE503
Features
•
•
•
•
•
•
Four internal PLLs
Internal non-volatile EEPROM
Fast (400kHz) mode I
2
C serial interface
Input frequency range: 1 MHz to 200 MHz
Output frequency range: 4.9 kHz to 200 MHz
Reference crystal input with programmable linear load
capacitance
– Crystal frequency range: 8 MHz to 50 MHz
•
Each PLL has a 7-bit reference divider and a 12-bit
feedback-divider
•
8-bit output-divider blocks
•
Fractional division capability on one PLL
•
Two of the PLLs support spread spectrum generation
capability
•
I/O Standards:
– Outputs - 3.3 V LVTTL/ LVCMOS
– Inputs - 3.3 V LVTTL/ LVCMOS
•
•
•
•
•
•
•
•
•
Programmable slew rate control
Programmable loop bandwidth
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with auto and manual switchover
options
Individual output enable/disable
Power-down mode
3.3V core V
DD
Available in VFQFPN package
-40 to +85 C Industrial Temp operation
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
1
IDT5V49EE503
REV Q 071015
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Configuration
OUT0
SD/OE
SEL0
SEL1
GND
SEL2
19
VDD
XOUT
XIN/REF
VDDx
CLKIN
GND
1
VDD
OUT3
OUT6
GND
AVDD
13
7
CLKSEL
OUT1
OUT2
VDD
SDAT
24-pin QFN
Pin Descriptions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Name
VDD
XOUT
XIN / REF
SCLK
VDD
I/O
O
I
Pin Type
Power
LVTTL
LVTTL
Power
Pin Description
Device power supply. Connect to 3.3V.
CRYSTAL_OUT -- Reference crystal feedback.
CRYSTAL_IN -- Reference crystal input or external reference clock
input.
Crystal oscillator power supply. Connect to 3.3V through 5
resistor. Use filtered analog power supply if available.
Input clock. Weak internal pull down resistor.
Connect to Ground.
Configurable clock output 1.
Configurable clock output 2.
Device power supply. Connect to 3.3V.
Device power supply. Connect to 3.3V.
Bidirectional I
2
C data.
I
2
C clock.
Input clock selector. Weak internal pull down resistor.
Device analog power supply. Connect to 3.3V. Use filtered analog
power supply if available.
Connect to Ground.
Configurable clock output 6.
Configurable clock output 3.
Device power supply. Connect to 3.3V.
VDDx
CLKIN
GND
OUT1
OUT2
VDD
VDD
SDAT
SCLK
CLKSEL
AVDD
GND
OUT6
OUT3
VDD
O
O
I/O
I
I
O
O
I
LVTTL
Power
LVTTL
LVTTL
Power
Power
Open Drain
LVTTL
LVTTL
Power
Power
LVTTL
LVTTL
Power
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
3
IDT5V49EE503
REV Q 071015
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin#
19
20
21
22
Pin Name
SEL2
SEL1
SEL0
SD/OE
I/O
I
I
I
I
Pin Type
LVTTL
LVTTL
LVTTL
LVTTL
Pin Description
Configuration select pin. Weak internal pull down resistor.
Configuration select pin. Weak internal pull down resistor.
Configuration select pin. Weak internal pull down resistor.
Enables/disables the outputs or powers down the chip. The SP bit
(0x02) controls the polarity of the signal to be either active HIGH or
LOW. (Default is active LOW.) Weak internal pull down resistor.
Configurable clock output 0.
Connect to Ground.
23
24
OUT0
GND
O
LVTTL
Power
1. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
2. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
3. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
4
IDT5V49EE503
REV Q 071015
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
PLL Features and Descriptions
7-bit
D
VCO
4-bit
A
12-bit
N
Sigm a-Delta
M odulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
(D)
1
Values
PLL0
PLL1
PLL2
PLL3
1 - 127
1 - 127
1 - 127
3 - 127
Multiplier
(M)
2
Values
10 - 8206
1 - 4095
1 - 4095
12 - 4095
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
Yes
Yes
Yes
Yes
Yes
No
No
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
5
IDT5V49EE503
REV Q 071015
京公网安备 11010802033920号
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