Junction Temperature ......................................................+150°C
Storage Temperature Range
............................
-65°C to +150°C
Lead Temperature (soldering, 10s)
.................................
+300°C
Soldering Temperature (reflow)
.......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 2)
20 TQFN-EP
Junction-to-Ambient Thermal Resistance (θ
JA
)
..........29°C/W
Junction-to-Case Thermal Resistance (θ
JC
)
.................2°C/W
Note 1:
Maximum continuous current at a given temperature must be calculated such that the maximum continuous power dissipation
for the package is not exceeded.
Note 2:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
S
= +2.7V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 3)
PARAMETER
Operating Voltage
Quiescent Current
Dynamic Average Supply
Current
Thermal Shutdown
Thermal-Shutdown Hysteresis
Power-On Reset
Power-On-Reset Hysteresis
SYMBOL
V
S
I
CC
I
S
T
SHD
T
SHDH
V
RST
V
RSTH
V
S
falling
1.8
I
OUT_
= 0, logic inputs = 0 or
V
S
,
RESET
= low
V
S
= 3.6V
V
S
= 5V
CONDITIONS
MIN
2.7
5
10
TYP
MAX
5.5
70
100
6
+160
20
2.05
140
2.3
UNITS
V
μA
mA
°C
°C
V
mV
f
SCLK
= 10MHz, f
DIN
= 0.5 x f
CLK
,
C
OUT
= 50pF, V
S
= 5.5V
DIGITAL INPUTS (SCLK, DIN,
CS, RESET,
PDCD, SPLD)
Input Logic-High Voltage
V
IH
V
IL
V
HYST
I
LEAK
C
IN
Input voltages = 0 or +5.5V
-1
10
V
S
= 2.7V to 3.6V
V
S
= 4.5V to 5.5V
V
S
= 2.7V to 3.6V
V
S
= 4.5V to 5.5V
230
+1
2.0
2.4
0.6
0.8
V
Input Logic-Low Voltage
Input Logic Hysteresis
Input Leakage Currents
Input Capacitance
V
mV
µA
pF
www.maximintegrated.com
Maxim Integrated │
2
MAX4896
Space-Saving, 8-Channel Relay/Load Driver
Electrical Characteristics (continued)
(V
S
= +2.7V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
T
J
= +25°C
T
J
= +125°C
T
J
= +150°C
T
J
= +25°C
T
J
= +125°C
T
J
= +150°C
-1
50
400
30
3
MIN
TYP
5
MAX
6
11
12
4
7
8
+1
75
960
μA
V
mA
pF
Ω
UNITS
RELAY OUTPUT DRIVERS (OUT1–OUT8)
I
OUT
= 50mA,
V
S
= 2.7V
OUT_ ON Resistance
R
ON
I
OUT
= 100mA,
V
S
= 4.5V
I
OUT
Off-Leakage Current
OUT Clamping Voltage
OUT Current-Limit Threshold
OUT Capacitance
DIAGNOSTIC
Open-Load Detection Voltage
Threshold
Open-Load Detection-Voltage-
Threshold Hysteresis
OUT_ Pulldown Current
Fault Delay/Filtering Time
DIGITAL OUTPUT (DOUT,
FLAG)
DOUT Low Voltage
DOUT High Voltage
FLAG
Low Voltage
FLAG
Off-Leakage Current
TIMING
From rising edge of
CS
at 50% to
V
OUT_
= 90%VP, VP = 15V, R
L
= 300Ω,
C
L
= 50pF, 2.7V ≤ V
S
< 3.6V
From rising edge of
CS
at 50% to
V
OUT_
= 90%VP, VP =16V, R
L
= 150Ω,
C
L
= 50pF, 4.5V ≤ V
S
≤ 5.5V
From rising edge of
CS
at 50% to
V
OUT_
= 10%VP, VP = 15V, R
L
= 300Ω,
C
L
= 50pF, 2.7V ≤ V
S
< 3.6V
From rising edge of
CS
at 50% to
V
OUT_
= 90%VP, VP = 16V, R
L
= 150Ω,
C
L
= 50pF, 4.5V < V
S
≤ 5.5V
20
μs
10
V
OL
V
OH
V
DS(OL)
V
DS(OLH)
I
PD(OL)
t
D(FAULT)
PDCD = low
From rising edge at
CS
at 50% to valid
diagnostic data
2.7V ≤ V
S
≤ 3.6V, I
SINK
= 0.3mA
4.5V ≤ V
S
≤ 5.5V, I
SINK
= 0.5mA
2.7V ≤ V
S
≤ 3.6V, I
SOURCE
= 0.25mA
4.5V ≤ V
S
≤ 5.5V, I
SOURCE
= 0.4mA
I
SINK
= 0.5mA
4.5V ≤ V
S
≤ 5.5V, V
FLAG
= 5.5V
-1
V
S
- 0.5
V
S
- 0.5
0.4
+1
150
30
OUT_ falling
0.75
1
40
300
90
500
280
1.15
V
mV
µA
µs
I
LEAK
V
CLAMP
I
LIM
PDCD = high or
RESET
= low, all outputs Off
(Note 4)
V
S
≥ 4.5V
V
OUT
= 16V, f = 1MHz
0.4
0.4
V
V
V
μA
Turn-On Time (OUT_)
t
ON
15
μs
10
Turn-Off Time (OUT_)
t
OFF
www.maximintegrated.com
Maxim Integrated │
3
MAX4896
Space-Saving, 8-Channel Relay/Load Driver
Electrical Characteristics (continued)
(V
S
= +2.7V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 3)
PARAMETER
SYMBOL
T
A
= +85°C
SCLK Frequency
f
SCLK
T
A
= +125°C
Cycle Time
t
CH
+ t
CL
t
CSS
t
CSH
t
CH
t
CL
t
DS
t
DH
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
50% of SCLK to 20% of
V
S
falling edge,
C
L
= 50pF, 50% at
SCLK to 80% of VS
rising edge
20% of V
S
to 70% of
V
S
, C
L
= 50pF (Note 5)
20% of V
S
to 70% of
V
S
, C
L
= 50pF (Note 5)
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
70
CONDITIONS
2.7V ≤ V
S
< 3.6V
4.5V ≤ V
S
≤ 5.5V
2.7V ≤ V
S
≤ 3.6V
4.5V ≤ V
S
≤ 5.5V
200
100
100
50
100
50
80
40
80
40
40
20
5
0
70
ns
30
2
2
2
2
0
MIN
0
TYP
MAX
6
11
5
10
ns
MHz
UNITS
CS
Fall-to-SCLK Rise Setup
ns
CS
Rise-to-SCLK Hold
ns
SCLK High Time
ns
SCLK Low Time
ns
Data Setup Time
ns
Data Hold Time
ns
SCLK Fall-to-DOUT Valid
t
DO
Rise Time (DIN, SCLK,
CS,
RESET)
Fall Time (DIN, SCLK,
CS,
RESET)
RESET
Min Pulse Width
t
SCR
μs
t
SCF
t
RW
μs
ns
Note 3:
Specifications at -40°C are guaranteed by design and not production tested.
Note 4:
The output stages are compliant with the transient immunity requirements, as specified in ISO 7637 Part 3 with test pulses
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