Low Skew, 1-to-8, Differential-to-LVDS
Clock
85408
DATA SHEET
General Description
The 85408 is a low skew, high performance 1-to-8
Differential-to-LVDS Clock Distribution Chip. The 85408 CLK, nCLK
pair can accept most differential input levels and translates them to
3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the 85408 provides a low power, low noise, low skew,
point-to-point solution for distributing LVDS clock signals.
Guaranteed output and part-to-part skew specifications make the
85408 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Eight differential LVDS output pairs
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL, SSTL,
HCSL) to LVDS levels without external bias networks
Translates any single-ended input signal to LVDS with resistor
bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 550ps (maximum)
Propagation delay: 2.4ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q7
nQ7
OE
GND
V
DD
V
DD
GND
V
DD
CLK
nCLK
Q0
nQ0
CLK
nCLK
85408
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
85408 Rev C 1/5/15
1
©2015 Integrated Device Technology, Inc.
85408 DATA SHEET
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11, 12
13, 14
15
16
17, 19, 20
18, 21
22
23, 24
Name
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
CLK
V
DD
GND
OE
nQ7, Q7
Output
Output
Output
Output
Output
Output
Output
Input
Input
Power
Power
Input
Output
Pullup
Pullup
Pulldown
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
Non-inverting differential clock input.
Positive supply pins.
Power supply ground.
Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH,
the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS /
LVTTL interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
4
51
51
Maximum
Units
pF
pF
k
k
Function Tables
Table 3A. Output Enable Function Table
Inputs
OE
0
1
Outputs
Q[0:7], nQ[0:7]
High-Impedance
Active (default)
Rev C 1/5/15
2
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK
85408 DATA SHEET
Table 3B. Clock Input Function Table
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q[0:7]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ[0:7]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section,
Wiring the Differential Input to Accept Single-Ended Levels.
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK
3
Rev C 1/5/15
85408 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
70°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
90
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
CLK
Input High Current
nCLK
CLK
I
IL
V
PP
V
CMR
Input Low Current
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
µA
µA
V
V
Units
µA
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Rev C 1/5/15
4
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK
85408 DATA SHEET
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
I
Oz
I
OFF
I
OSD
I
OS
/I
OSB
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage
Power Off Leakage
Differential Output Short
Circuit Current
Output Short Circuit Current
Test Conditions
R
L
= 100
R
L
= 100
R
L
= 100
R
L
= 100
-10
-1
1.125
1.4
Minimum
250
Typical
400
Maximum
600
50
1.6
50
+10
+1
-5.5
-12
Units
mV
mV
V
mV
µA
µA
mA
mA
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
t
PZL,
t
PZH
t
PLZ,
t
PHZ
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
20% to 80%
50
45
156.25MHz,
Integration Range: (12kHz – 20MHz)
1.6
167
50
550
600
55
5
5
Test Conditions
Minimum
Typical
Maximum
700
2.4
Units
MHz
ns
fs
ps
ps
ps
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at f
622MHz
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crossing
point of the input to the differential output crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK
5
Rev C 1/5/15
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