74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
Rev. 2 — 22 November 2012
Product data sheet
1. General description
The 74HC4052-Q100; 74HCT4052-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance
with JEDEC standard no. 7A.
The 74HC4052-Q100; 74HCT4052-Q100 is a dual 4-channel analog
multiplexer/demultiplexer with common select logic. Each multiplexer has four
independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The
common channel select logics include two digital select inputs (pins S0 and S1) and an
active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected
(low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in
the high-impedance OFF-state, independent of pins S0 and S1.
V
CC
and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for the 74HC4052-Q100, and 4.5 V to 5.5 V
for the 74HCT4052-Q100. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing
between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed
10.0 V. For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND
(typically ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
CDM AEC-Q100-011 revision B exceeds 1000 V
Multiple package options
NXP Semiconductors
74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC4052D-Q100
74HCT4052D-Q100
74HC4052PW-Q100
74HCT4052PW-Q100
74HC4052BQ-Q100
74HCT4052BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SO16
Description
plastic small outline package; 16 leads; body
width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual-in line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
10
13
1Z
1Y0
10
9
S0
S1
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
6
E
2Z
001aah824
0
1
G4
4
×
9
6
12
14
15
11
1
5
2
4
13
3
0
3
MDX
0
1
2
3
1
5
2
4
12
14
15
11
001aah825
2Y3
3
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT4052_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 22 November 2012
2 of 26
NXP Semiconductors
74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
nYn
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
nZ
V
EE
mnb043
Fig 3.
Schematic diagram (one switch)
V
DD
16
13
12
1Z
1Y0
14
1Y1
15
S0
10
1Y2
11
9
LOGIC
LEVEL
CONVERSION
1-OF-4
DECODER
1
1Y3
S1
2Y0
E
6
5
2Y1
2
2Y2
4
2Y3
3
8
V
SS
7
V
EE
2Z
001aah872
Fig 4.
Functional diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
74HC_HCT4052_Q100
Product data sheet
Rev. 2 — 22 November 2012
3 of 26
NXP Semiconductors
74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4052-Q100
74HCT4052-Q100
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
1
2
3
4
5
6
7
8
aaa-003162
74HC4052-Q100
74HCT4052-Q100
terminal 1
index area
2Y2
2
3
4
5
6
7
8
GND
S1
9
V
CC(1)
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
2Y0
1
2Z
2Y3
2Y1
E
V
EE
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
9
S1
aaa-003163
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5.
Pin configuration for SO16 and TSSOP16
Fig 6.
Pin configuration for DHVQFN16
6.2 Pin description
Table 2.
Symbol
2Y0, 2Y1, 2Y2, 2Y3
1Z, 2Z
E
V
EE
GND
S0, S1
1Y0, 1Y1, 1Y2, 1Y3
V
CC
Pin description
Pin
1, 5, 2, 4
13, 3
6
7
8
10, 9
12, 14, 15, 11
16
Description
independent input or output
common input or output
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input
independent input or output
positive supply voltage
74HC_HCT4052_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 22 November 2012
4 of 26
NXP Semiconductors
74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3.
Input
E
L
L
L
L
H
[1]
Function table
[1]
Channel on
S1
L
L
H
H
X
S0
L
H
L
H
X
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to V
EE
= GND (ground = 0 V).
Symbol
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
P
[1]
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
power dissipation
Conditions
[1]
Min
0.5
-
-
-
-
-
-
65
[2]
Max
+11.0
20
20
25
20
50
50
+150
500
100
Unit
V
mA
mA
mA
mA
mA
mA
C
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
0.5
V < V
SW
< V
CC
+ 0.5 V
-
-
per switch
To avoid drawing V
CC
current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no V
CC
current flows out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed V
CC
or V
EE
.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 package: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 package: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
74HC_HCT4052_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 22 November 2012
5 of 26
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