1:4 LVDS Output 1.8V Fanout Buffer
IDT8P34S1204I
DATA SHEET
General Description
The IDT8P34S1204I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1204I is characterized to operate from a 1.8V power
supply. Guaranteed low output-to-output and part-to-part skew
characteristics make the IDT8P34S1204I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Four low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz
LVCMOS/LVTTL interface levels for the control input select
Output skew: 10ps (typical)
Propagation delay: 400ps (maximum)
Low additive phase jitter, RMS; f
REF
= 156.25MHz,
10kHz - 20MHz: 43fs (typical)
Device current consumption (I
DD
): 78mA (maximum)
Full 1.8V supply voltage
lead-free (RoHS 6), 16-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
V
DD
Pin Assignment
nQ1
nQ0
10
Q1
12
11
CLK0
nCLK0
Pulldown
Pullup/Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q2
13
nQ2
14
Q0
9
8
V
REF
7
nCLK0
6
CLK0
5
V
DD
4
0
V
DD
1
Q3
15
nQ3
16
1
2
3
f
REF
CLK1
GND
SEL
CLK1
nCLK1
Pulldown
Pullup/Pulldown
SEL
V
REF
Pulldown
Voltage
Reference
IDT8P34S1204I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
1.7mm x 1.7mm ePad Size
NL Package
Top View
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
1
©2014 Integrated Device Technology, Inc.
nCLK1
IDT8P34S1204I Data Sheet
1:4 LVDS Output 1.8V Fanout Buffer
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Note1.
Number
1
2
3
4
5
6
7
Name
GND
SEL
CLK1
nCLK1
V
DD
CLK0
nCLK0
Power
Input
Input
Input
Power
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Power supply ground.
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Power supply pin.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Bias voltage reference. Provides an input bias voltage for the
CLK[0:1], nCLK[0:1] input pairs in AC-coupled applications. Refer to
Figures 2B and 2C
for applicable AC-coupled input interfaces.
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
8
V
REF
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Output
9, 10
11, 12
13, 14
15, 16
1.
Output
Output
Output
Output
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function Table
Note1.
Input
SEL
0 (default)
1
1.
Operation
CLK0, nCLK0 is the selected differential clock input.
CLK1, nCLK1 is the selected differential clock input.
SEL is an asynchronous control.
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
2
©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet
1:4 LVDS Output 1.8V Fanout Buffer
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
Note1.
ESD - Charged Device Model
Note 1
1.
According to JEDEC JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±2mA
125°C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Q0 to Q3 terminated 100 between nQx, Qx
Test Conditions
Minimum
1.71
Typical
1.8
65
Maximum
1.89
78
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage, Note 1
Input High Current
Input Low Current
SEL
SEL
V
DD
= V
IN
= 1.89V
V
DD
= 1.89V, V
IN
= 0V
-10
Test Conditions
Minimum
0.65 * V
DD
-0.3
Typical
Maximum
V
DD
+ 0.3
0.35 * V
DD
150
Units
V
V
µA
µA
Note 1: VIL should not be less than -0.3V and VIH should not be higher than V
DD
.
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
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©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet
1:4 LVDS Output 1.8V Fanout Buffer
Table 4C. Differential Inputs Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
CLK0, nCLK0,
CLK1, nCLK1
CLK0, CLK1
nCLK0, nCLK1
Test Conditions
V
IN
= V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
I
REF
= +100µA, V
DD
= 1.8V
V
DD
= 1.89V
-10
-150
0.9
0.2
0.9
1.30
1.0
V
DD
– (V
PP
/2)
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
I
IL
V
REF
V
PP
V
CMR
1.
2.
3.
Reference Voltage for Input
Bias
Note1.
Peak-to-Peak Voltage
Note3.
Common Mode Input
Voltage
Note2. Note3.
V
REF
specification is applicable to the AC-coupled input interfaces shown in
Figures 2B and 2C.
Common mode input voltage is defined as crosspoint voltage.
V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
Table 4D. LVDS DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note1.
Symbol
V
OD
V
OD
V
OS
V
OS
1.
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.00
Test Conditions
outputs loaded with 100
Minimum
247
Typical
Maximum
454
50
1.40
50
Units
mV
mV
V
mV
Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance).
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
4
©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet
1:4 LVDS Output 1.8V Fanout Buffer
AC Electrical Characteristics
Table 5. AC Electrical Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note1.
Symbol
f
REF
V/t
Parameter
Input
Frequency
Input
Edge Rate
CLK[0:1],
nCLK[0:1]
CLK[0:1],
nCLK[0:1]
CK[0:1], nCLK[0:1] to any Qx, nQx
1.5
Test Conditions
Minimum
Typical
Maximum
1.2
Units
GHz
V/ns
t
PD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
Propagation
Delay
Note2. Note3.
Output Skew
Note4. Note5.
Input Skew
Pulse Skew
Part-to-Part Skew
Note6.
150
10
400
40
20
ps
ps
ps
ps
ps
fs
fs
fs
fs
fs
fs
fs
fs
fs
ps
ps
dB
f
REF
= 100MHz
20
250
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
10% to 90% outputs loaded with 100
t
R
/ t
F
MUX
ISOLATION
1.
Output Rise/ Fall Time
20% to 80% outputs loaded with 100
Mux Isolation
Note7.
f
REF
= 100MHz
74
57
57
65
43
43
69
47
47
215
120
73
100
80
80
90
70
70
90
60
60
400
260
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
2.
3.
4.
5.
6.
7.
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Measured from the differential input crossing point to the differential output crosspoint.
Input V
PP
is 0.4V.
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
Qx, nQx outputs measured differentially. See
MUX Isolation diagram
in the
Parameter Measurement Information section.
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
5
©2014 Integrated Device Technology, Inc.
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