CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications
SYMBOL
T
Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 210MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted
COMMENT
MIN
TYP
MAX
UNIT
PARAMETER
FULL CHANNEL CHARACTERISTICS
ADC Resolution
Missing Codes
Conversion Rate
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
Gain Adjustment Range
Gain Adjustment Resolution
Gain Matching Between Channels
Percent of full scale
Guaranteed monotonic
Per Channel
10
±0.6
±1.25
±6
8
±1
±0.125
±127
5
±0.5
8
None
210
+1.0
-0.9
±3.25
MHz
LSB
LSB
dB
Bits
%
LSB
LSB
ns
Bits
Full Channel Offset Error, ABLC™ enabled ADC LSBs, over time and temperature
Offset Adjustment Range, ABLC™
enabled or disabled
Overvoltage Recovery Time
ADC LSBs (see ABLC™ applications
information section)
For 150% overrange, maximum bandwidth
setting
ANALOG VIDEO INPUT CHARACTERISTICS (R
IN
1, G
IN
1, B
IN
1, R
IN
2, G
IN
2, B
IN
2)
Input Range
Input Bias Current
Input Capacitance
Full Power Bandwidth
INPUT CHARACTERISTICS (SOG
IN
1, SOG
IN
2)
V
IH
/V
IL
Input Threshold Voltage
Hysteresis
Input capacitance
INPUT CHARACTERISTICS (HSYNC
IN
1, HSYNC
IN
2)
V
IH
/V
IL
Input Threshold Voltage
Hysteresis
R
IN
Input impedance
Programmable - See Register Listing for
Details
Centered around threshold voltage
0.4 to 3.2
240
1.2
V
mV
kΩ
Programmable - See Register Listing for
Details
Centered around threshold voltage
0 to
-0.3
40
5
V
mV
pF
Programmable
DC restore clamp off
0.35
0.7
±0.01
5
780
1.4
±1
V
P-P
µA
pF
MHz
3
FN8219.3
March 8, 2006
X98021
Electrical Specifications
SYMBOL
Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 210MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted
(Continued)
COMMENT
MIN
TYP
5
MAX
UNIT
pF
PARAMETER
Input capacitance
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV
IN
, RESET)
V
IH
V
IL
I
Input HIGH Voltage
Input LOW Voltage
Input leakage current
Input capacitance
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC
IN
1, VSYNC
IN
2)
V
T
+
V
T
-
I
Low to High Threshold Voltage
High to Low Threshold Voltage
Input leakage current
Input capacitance
DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK)
V
OH
V
OL
Output HIGH Voltage, I
O
= 16mA
Output LOW Voltage, I
O
= -16mA
2.4
0.4
V
V
±10
5
1.45
0.95
V
V
nA
pF
RESET has a 70kΩ pullup to V
D
±10
5
2.0
0.8
V
V
nA
pF
DIGITAL OUTPUT CHARACTERISTICS (R
P
, G
P
, B
P
, R
S
, G
S
, B
S
, HS
OUT
, VS
OUT
, HSYNC
OUT
, VSYNC
OUT
)
V
OH
V
OL
R
TRI
Output HIGH Voltage, I
O
= 8mA
Output LOW Voltage, I
O
= -8mA
Pulldown to GND
D
when three-state
R
P
, G
P
, B
P
, R
S
, G
S
, B
S
only
58
2.4
0.4
V
V
kΩ
DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLK
OUT
)
V
OH
V
OL
Output HIGH Voltage, I
O
= 4mA
Output LOW Voltage, I
O
= -4mA
XTALCLK
OUT
only; SDA is open-drain
2.4
0.4
V
V
POWER SUPPLY REQUIREMENTS
V
A
V
D
V
X
I
A
I
D
I
X
P
D
Analog Supply Voltage
Digital Supply Voltage
Crystal Oscillator Supply Voltage
Analog Supply Current
Digital Supply Current
Crystal Oscillator Supply Current
Total Power Dissipation
Operating (average)
Power-down Mode
Θ
JA
Thermal Resistance, Junction to Ambient
Operating
Operating (grayscale)
3
3
3
3.3
3.3
3.3
185
145
0.7
1.1
50
30
3.6
3.6
3.6
200
160
2
1.3
80
V
V
V
mA
mA
mA
W
mW
°C/W
AC TIMING CHARACTERISTICS
PLL Jitter
Sampling Phase Steps
Sampling Phase Tempco
Sampling Phase Differential Nonlinearity
HSYNC Frequency Range
f
XTAL
Crystal Frequency Range
Degrees out of 360°
10
23
25
5.6° per step
64
±1
±3
150
27
ps/°C
°
kHz
MHz
250
450
ps p-p
4
FN8219.3
March 8, 2006
X98021
Electrical Specifications
SYMBOL
t
SETUP
t
HOLD
Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 210MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted
(Continued)
COMMENT
MIN
1.3
2.0
TYP
MAX
UNIT
ns
ns
PARAMETER
DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
DATA valid after rising edge of DATACLK
15pF DATACLK load, 15pF DATA load
(Note 1)
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
f
SCL
SCL Clock Frequency
Maximum width of a glitch on SCL that will
be suppressed
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
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Microcontroller MCU
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