output pairs (pin selectable output type), and uses
external feedback for “zero delay” clock
regeneration. In PCI Express and Ethernet
applications, 100MHz and 125MHz are the most commonly used
reference clock frequencies and each of the four output pairs can
be independently set for either 100MHz or 125MHz. With an
output frequency range of 98MHz to 165MHz, the device is also
suitable for use in a variety of other applications such as Fibre
Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS
Input/Output pair is useful in backplane applications when the
reference clock can either be local (on the same board as the
ICS8743004I) or remote via a backplane connector. In output
mode, an input from a local reference clock applied to the
CLK/nCLK input pins is translated to M-LVDS and driven out to the
MLVDS/nMLVDS pins. In input mode, the internal M_LVDS driver
is placed in Hi-Z state using the OE_MLVDS pin and
MLVDS/nMLVDS pin then becomes an input (e.g. from a
backplane).
Features
•
•
•
•
•
•
•
•
•
•
•
•
Four differential output pairs with selectable pin type: LVDS or
LVPECL. Each output pair is individually selectable for 100MHz
or 125MHz (for PCIe and Ethernet applications).
One differential clock input pair CLK/nCLK can accept the
following differential input levels: LVPECL, LVDS, M-LVDS,
LVHSTL, HCSL
One M-LVDS I/O (MLVDS/nMLVDS)
Output frequency range: 98MHz - 165MHz
Input frequency range: 19.6MHz - 165MHz
VCO range: 490MHz - 660MHz
PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
External feedback for “zero delay” clock regeneration
RMS phase jitter @ 125MHz (1.875MHz – 20MHz):
0.57ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
ICS
The ICS8743004I uses very low phase noise FemtoClock™
technology, thus making it ideal for such applications as PCI
Express Generation 1 and 2 as well as for Gigabit Ethernet, Fibre
Channel, and 10 Gigabit Ethernet. It is packaged in a 40-VFQFN
package (6mm x 6mm).
Pin Assignment
PDIV1
PDIV0
nCLK
V
DDO
Q0
V
DDA
CLK
nQ0
Q1
nQ1
V
DD
OE_MLVDS
MLVDS
nMLVDS
PLL_SEL
FBO_DIV
MR
OE0
OE1
GND
40 39 38 37 36 35 34 33 32 31
1
30
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
GND
QDIV0
QDIV1
QDIV2
FBI_DIV0
FBI_DIV1
QDIV3
nFBIN
V
DD
FBIN
V
DDO
Q2
nQ2
GND
Q3
nQ3
FBOUT
nFBOUT
V
DDO
Q_TYPE
29
28
27
26
25
24
23
22
21
ICS8743004I
40-Lead VFQFN
6mm x 6mm x 0.925mm package body
K Package
Top View
The
Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 1
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Block Diagram
2
OE1:0 (PU, PU)
PDIV1 (PD)
PDIV0 (PD)
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
QDIV0
0 ÷4 (default)
1 ÷5
QDIV0 (PD)
Q0
nQ0
QDIV1 (PD)
QDIV1
0 ÷4 (default)
1 ÷5
Q1
nQ1
QDIV2 (PD)
VCO
490-660 MHz
QDIV2
0 ÷4 (default)
1 ÷5
Q2
nQ2
QDIV3 (PD)
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
QDIV3
0 ÷4 (default)
1 ÷5
Q3
nQ3
CLK (PD)
nCLK (PU/PD)
MR (PD)
OE_MLVDS (PU)
MLVDS
nMLVDS
0
PD
FBI_DIV1 (PU)
FBI_DIV0 (PU)
1
FBIN (PD)
nFBIN (PU/PD)
FBO_DIV (PD)
PLL_SEL (PU)
FBO_DIV
0 ÷4 (default)
1 ÷5
FBOUT
nFBOUT
Q_TYPE (PD)
MR (PD)
PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)
PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)
IDT™ / ICS™
LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 2
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 11
Name
V
DD
Power
Type
Description
Core supply pins.
Active High Output Enable. When HIGH, the M-LVDS output driver is active
and provides a buffered copy of reference clock applied the CLK/nCLK input
to the MLVDS/nMLVDS output pins. The MLVDS/nMLVDS frequency equals
the CLK/ nCLK frequency divided by the PDIV Divider value (selectable ÷1,
÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is placed into a Hi-Z state
and the MLVDS/nMLVDS pins can accept a differential input.
LVCMOS/LVTTL interface levels.
Non-Inverting M-LVDS input/output. The input/output state is determined by
the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and
drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin
is an input and can accept the following differential input levels: M-LVDS,
LVDS, LVPECL, HSTL, HCSL.
Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives
the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input
and can accept the following differential input levels: M-LVDS, LVDS,
LVPECL, HSTL, HCSL. The output driver is always M-LVDS and is not
affected by the state of the Q-TYPE pin which affects Q0/nQ0:Q3/nQ3, and
FBOUT/nFBOUT.
PLL select. Determines if the PLL is in bypass or enabled mode (default). In
enabled mode, the output frequency = VCO frequency/QDIV divider. In
bypass mode, the output frequency = reference clock frequency/
(PDIV*QDIV). LVCMOS/LVTTL interface levels.
Output Divider Control for the feedback output pair, FBOUT/nFBOUT.
Determines if the output divider = ÷4 (default), or ÷5.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the Qx/nQx outputs to drive Hi-Z. Note that assertion of MR overrides
the OE[0:2] control pins and all outputs are disabled. When logic LOW, the
internal dividers are enabled and the state of the outputs is determined by
OE[0:2]. MR must be asserted on power-up to ensure outputs phase aligned.
LVCMOS/LVTTL interface levels.
Output Enable. Together with OE1, determines the output state of the outputs
with the default state: all output pairs switching. When an LVDS or LVPECL
output pair is disabled, the disable state is Qx/nQx = Hi-Z. It should also be
noted that the feedback output pins (FBOUT/nFBOUT) are always switching
and are not affected by the state of OE[0:1]. Refer to table 3B for truth table.
LVCMOS/LVTTL Interface levels.
Output Enable. Together with OE0, determines the output state of the outputs
with the default state: all output pairs switching. When an LVDS or LVPECL
output pair is disabled, the disable state is Qx/nQx = Hi-Z. It should also be
noted that the feedback output pins (FBOUT/nFBOUT) are always switching
and are not affected by the state of OE[1:0]. Refer to table 3B for truth table.
LVCMOS/LVTTL Interface levels
Power supply ground.
Pullup
Feedback Input Divide Select 0. Together with FB_DIV1, determines the
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