1-to-10, Differential HCSL Fanout Buffer
Datasheet
851010
General Description
The 851010 is a 1-to-10 Differential HCSL Fanout Buffer. The
851010 is designed to translate any differential signal levels to
differential HCSL output levels. An external reference resistor is
used to set the value of the current supplied to an external load. The
load resistor value is chosen to equal the value of the characteristic
line impedance of 50. The 851010 is characterized at an operating
supply voltage of 3.3V.
The differential HCSL outputs, accurate crossover voltage and
symmetric duty cycle makes the 851010 ideal for interfacing to PCI
Express and FBDIMM applications.
Features
•
•
•
•
•
•
•
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Ten differential HCSL outputs
Translates any differential input signal (LVPECL, LVHSTL, LVDS,
HCSL) to HCSL levels without external bias networks
Maximum output frequency: 250MHz
Output skew: 165ps (maximum)
Part-to-part skew: 250ps (maximum)
Output drift: 140ps (maximum)
V
OH
: 850mV (maximum)
Full 3.3V supply voltage
Available in lead-free (RoHS 6) package
0°C to 70°C ambient operating temperature
Block Diagram
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
IREF
Q9
nQ9
Q8
nQ8
Q7
nQ7
Q6
nQ6
Q5
nQ5
Pin Assignment
nCLK
V
DD
GND
nQ8
Q9
Q8
CLK
nQ9
32 31 30 29 28 27 26 25
Q0
nQ0
V
DD
Q1
nQ1
Q2
nQ2
V
DD
1
2
3
4
5
6
7
8
9
GND
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
V
DD
IREF
nQ4
nQ3
Q3
V
DD
Q4
nQ7
Q7
V
DD
nQ6
Q6
nQ5
Q5
V
DD
851010
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc
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December 3, 2015
851010 Datasheet
Table 1. Pin Descriptions
Number
1, 2
3, 8, 13, 14,
17, 22, 30
4, 5
6, 7
9, 25
10
11, 12
15, 16
18, 19
20, 21
23, 24
26
27
28, 29
31, 32
Name
Q0, nQ0
V
DD
Q1, nQ1
Q2, nQ2
GND
IREF
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
CLK
nCLK
Q8, nQ8
Q9, nQ9
Type
Output
Power
Output
Output
Power
Input
Output
Output
Output
Output
Output
Input
Input
Output
Output
Description
Differential output pair. Differential HCSL interface levels.
Positive supply pins.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Power supply ground.
Reference current input. Used to set the output current. Connect to 950
resistor to ground.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Non-inverting differential input.
Inverting differential clock input.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Output Driver Current
The 851010 outputs are HCSL differential current dr ive with
the current being set with a resistor from I
REF
to ground. For
a
single load
and a 50 pc board trace, the drive current would
typically be set with a R
REF
of 950 which products an I
REF
of 1.16mA.
The I
REF
is multiplied by a current mirror to an output drive of
12*1.16mA or 13.90mA. See
Figure 1
for current mirror and output
drive details.
I
REF
R
REF
950Ω
R
L
R
L
Figure 1. HCSL Current Mirror and Output Drive
©2015 Integrated Device Technology, Inc
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December 3, 2015
851010 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
65.7°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Core Supply Voltage
Power Supply Current; NOTE 1
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
105
Units
V
mA
NOTE 1: Measured using 200MHz input frequency.
Table 2B. Differential DC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
CLK, nCLK
CLK, nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
0.15
GND + 0.5
Minimum
Typical
Maximum
5
5
1.3
V
DD
– 0.85
Units
µA
µA
V
V
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
©2015 Integrated Device Technology, Inc
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December 3, 2015
851010 Datasheet
AC Electrical Characteristics
Table 3. HCSL AC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
tsk(drift)
V
MAX
V
MIN
V
CROSS
V
CROSS
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS
Output Drift; NOTE 5
Absolute Max Output Voltage; NOTE 6
Absolute Min Output Voltage; NOTE 6
Absolute Crossing Voltage;
NOTE 7, 8, 9
Total Variation of V
CROSS
over all
edges; NOTE 7, 8, 10
Rise/Fall Edge Rate; NOTE 11, 12
Output Duty Cycle; NOTE 13
0.6
47
ƒ
150MHz
ƒ
150MHz
500
-150
250
CLK = 200MHz, Integration
Range: 12kHz – 30MHz
0.24
140
850
150
550
140
4.0
53
Measured on at V
OX
Measured on at V
OX
1.5
Test Conditions
Minimum
Typical
Maximum
250
2.75
165
250
Units
MHz
ns
ps
ps
ps
ps
mV
mV
mV
mV
V/ns
%
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE:
Current adjust set for V
OH
= 0.7V. Measurements refer to PCIEX outputs only.
NOTE:
Characterized using an R
REF
value of 950
resistor.
NOTE 1:
Measured from the differential input cross point to the differential output crossing point.
NOTE 2:
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross point.
NOTE 3:
This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4:
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 5:
Output Drift is measured as the change in the time placement of the differential cross point for each output on a given device due to
a change in temperature and supply voltage. Measured at the differential cross point.
NOTE 6:
Measurement using R
REF
= to 950, R
LOAD
= to 50.
NOTE 7:
Measurement taken from single-ended waveform.
NOTE 8:
Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 9:
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10:
Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11:
Measurement taken from differential waveform.
NOTE 12:
Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 13:
Assuming 50% input duty cycle. Data taken at ƒ
200MHz, unless otherwise specified.
©2015 Integrated Device Technology, Inc
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December 3, 2015
851010 Datasheet
Parameter Measurement Information
3.3V±5%
V
DD
SCOPE
VDD
33Ω
49.9Ω
50Ω
Measurement
Point
VDD
50Ω
HCSL
33Ω
GND
49.9Ω
50Ω
2pF
Measurement
Point
GND
2pF
0V
HCSL
50Ω
IREF
950Ω
This load condition is used for I
DD,
tsk(pp), tjit(Ø), t
PD
and tsk(o)
measurements.
HCSL Output Load AC Test Circuit
HCSL Output Load AC Test Circuit
VDD
nQx
Qx
V
PP
nCLK
Cross Points
V
CMR
nQy
Qy
CLK
GND
Differential Input Levels
Output Skew
nQx
Qx
nQy
Qy
Par t 1
nCLK
CLK
Par t 2
nQ[0:9]
Q[0:9]
tsk(pp)
t
PD
Part-to-Part Skew
Propagation Delay
©2015 Integrated Device Technology, Inc
5
December 3, 2015
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