CD4027BMS
December 1992
CMOS Dual J-K
Master-Slave Flip-Flop
Pinout
CD4027BMS
TOP VIEW
Features
• High Voltage Type (20V Rating)
• Set - Reset Capability
• Static Flip-Flop Operation - Retains State Indefinitely
with Clock Level Either “High” or “Low”
• Medium Speed Operation - 16MHz (typ.) Clock Toggle
Rate at 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested For Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Q2 1
Q2 2
CLOCK 2 3
RESET 2 4
K2 5
J2 6
SET 2 7
VSS 8
16 VDD
15 Q1
14 Q1
13 CLOCK 1
12 RESET 1
11 K1
10 J1
9 SET 1
Functional Diagram
SET 1
VDD
16
9
J1 10
K1 11
CLOCK1 13
F/F1
15 Q1
14 Q1
Applications
• Registers, Counters, Control Circuits
RESET1 12
SET2
J2
K2
7
6
5
3
F/F2
2 Q2
1 Q2
Description
CD4027BMS is a single monolithic chip integrated circuit con-
taining two identical complementary-symmetry J-K master-
slave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals
are provided as outputs. This input-output arrangement pro-
vides for compatible operation with the Intersil CD4013B dual D
type flip-flop.
The CD4027BMS is useful in performing control, register, and
toggle functions. Logic levels present at the J and K inputs
along with internal self-steering control the state of each flip-
flop; changes in the flip-flop state are synchronous with the pos-
itive-going transition of the clock pulse. Set and reset functions
are independent of the clock and are initiated when a high level
signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
H4T
Frit Seal DIP
H1E
Ceramic Flatpack H6W
CLOCK2
RESET 2
4
8
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3302
7-780
Specifications CD4027BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
Ceramic DIP and FRIT Package . . . . . 80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
VIL
VIH
VIL
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25
o
C,
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
MIN
-
-
-
-100
-1000
-100
-
-
-
-
14.95
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
MAX
2
200
2
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+125
o
C,
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
-55
o
C
VOH > VOL <
VDD/2 VDD/2
-
3.5
-
11
1.5
-
4
-
V
V
V
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-781
Specifications CD4027BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
TPHL3
VDD = 5V, VIN = VDD or GND
9
10, 11
TTLH
TTHL
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25 C
+125
o
C,
-55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
o
LIMITS
MIN
-
-
-
-
-
-
-
-
3.5
3.5/1.35
MAX
300
405
300
405
400
540
200
270
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay
Clock To Q, Q
Propagation Delay
Set To Q Reset To Q
Propagation Delay
Set To Q, Reset To Q
Transition Time
SYMBOL
TPHL1
TPLH1
TPLH2
CONDITIONS
(NOTE 1, 2)
VDD = 5V, VIN = VDD or GND
Maximum Clock Input
Frequency
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-55
o
C
MIN
-
-
-
-
-
-
-
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
-
-
MAX
1
30
2
60
2
120
50
50
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
UNITS
µA
µA
µA
µA
µA
µA
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
7-782
Specifications CD4027BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH15
CONDITIONS
VDD =15V, VOUT = 13.5V
NOTES
1, 2
TEMPERATURE
+125
o
C
-55
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Clock To Q, Q
Propagation Delay
Set To Q, Reset To Q
Propagation Delay
Set To Q, Reset To Q
Transition Time
VIL
VIH
TPHL1
TPLH1
TPLH2
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TPHL3
VDD = 10V
VDD = 15V
TTHL
TTLH
FCL
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TS
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Set or Reset
Pulse Width
TW
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width
TW
VDD = 5V
VDD = 10V
VDD = 15V
Clock Input Rise Or Fall
Time (Note 5)
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propa-
gation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 20V, VIN = VDD or GND
NOTES
1, 4
TEMPERATURE
+25
o
C
MIN
-
MAX
7.5
UNITS
µA
CIN
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
7
-
-
-
-
-
-
-
-
8
12
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-2.4
-4.2
3
-
130
90
130
90
170
120
100
80
-
-
200
75
50
180
80
50
140
60
40
45
5
2
7.5
UNITS
mA
mA
V
V
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
pF
Maximum Clock Input
Frequency Toggle Mode
Input TR, TF = 5ns
Minimum Data Setup
Time
7-783
Specifications CD4027BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
V
V
V
V
V
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
±
0.2µA
±
20% x Pre-Test Reading
±
20% x Pre-Test Reading
DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
MIL-STD-883
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
Subgroups 1, 2, 3, 9, 10, 11
IDD, IOL5, IOH5A
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
5005
TEST
PRE-IRRAD
1, 7, 9
POST-IRRAD
Table 4
READ AND RECORD
PRE-IRRAD
1, 9
POST-IRRAD
Table 4
CONFORMANCE GROUPS
Group E Subgroup 2
7-784
Renesas Electronics MCUs
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