CD4089BFMSR datasheet, PDF - EEWORLD Datasheet

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CD4089BFMSR: Description4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, FRIT SEALED, DIP-16; Categorylogic logic; File Size94KB，10 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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CD4089BFMSR Overview

4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, FRIT SEALED, DIP-16

CD4089BFMSR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1530798642
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	not_compliant
Counting direction	UP
series	4000/14000/40000
JESD-30 code	R-GDIP-T16
JESD-609 code	e0
length	19.05 mm
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Operating mode	SYNCHRONOUS
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5/15 V
propagation delay (tpd)	405 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	5.08 mm
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
Trigger type	NEGATIVE EDGE
width	11.049 mm
minfmax	0.89 MHz

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CD4089BMS

December 1992

CMOS Binary Rate Multiplier

conjunction with an up/down counter and control logic used

to perform arithmetic operations (adds, subtract, divide, raise

to a power), solve algebraic and differential equations,

generate natural logarithms and trigometric functions, A/D

and D/A conversions, and frequency division.

For words of more than 4 bits, CD4089BMS devices may be

cascaded in two different modes: an Add mode and a Multi-

ply mode (see Figures 3 and 4). In the Add mode some of

the gaps left by the more signiﬁcant unit at the count of 15

are ﬁlled in by the less signiﬁcant units. For example, when

two units are cascaded in the Add mode and programmed to

11 and 13, respectively, the more signiﬁcant unit will have 11

output pulses for every 16 input pulses and the other unit will

have 13 output pulses for every 256 input pulses for a total of

189

256

Features

• High Voltage Type (20V Rating)

• Cascadable in Multiples of 4 Bits

• Set to “15” Input and “15” Detect Output

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

In the Multiply mode the fraction programmed into the ﬁrst

rate multiplier is multiplied by the fraction programmed into

the second multiplier. Thus the output rate will be

143

256

Applications

• Numerical Control

• Instrumentation

• Digital Filtering

• Frequency Synthesis

The CD4089BMS has an internal synchronous 4 bit counter

which, together with one of the four binary input bits, pro-

duces pulse trains as shown in Figure 6.

If more than one binary input bit is high, the resulting pulse

train is a combination of the separate pulse trains as shown

in Figure 6.

The CD4089BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4W

H2R

H6P

Description

CD4089BMS is a low power 4 bit digital rate multiplier that

provides an output pulse rate that is the clock-input-pulse

rate multiplied by

times the binary input. For example,

when the binary input number is 13, there will be 13 output

pulses for every 16 input pulses. This device may be used in

Pinout

CD4089BMS

TOP VIEW

Functional Diagram

CLOCK

“15” OUT 1

C 2

D 3

16 VDD

15 B

14 A

13 CLEAR

12 CASCADE

11 INHIBIT IN (CARRY)

10 STROBE

9 CLOCK

VDD = 16

VSS = 8

INHIBIT

(CARRY) IN

SET TO

“15”

CLEAR

4 BIT

BINARY

COUNTER

BINARY RATE

SELECT INPUTS

A B C D

14 15 2 3

RATE

SELECT

LOGIC

STROBE

CASCADE

OUT

SET TO “15” 4

OUT 5

OUT 6

INHIBIT OUT (CARRY) 7

VSS 8

RATE

OUTPUTS

“15” OUT

INHIBIT (CARRY) OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number

3329

7-1064

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