Features ................................................................................................................................................................ 6
General Description .............................................................................................................................................. 7
Branch Metric Unit (BMU) ............................................................................................................................ 9
Add, Compare, and Select Unit (ACS)....................................................................................................... 10
Traceback Unit (TBU) ................................................................................................................................ 10
Memory Management Unit (MMU)............................................................................................................. 10
Bit Error Rate Monitor (BER)...................................................................................................................... 10
Other Modules............................................................................................................................................ 10
Configuring the Block Viterbi Decoder ................................................................................................................ 10
Data Type................................................................................................................................................... 12
Signal Descriptions ............................................................................................................................................. 12
Interfacing with the Block Viterbi Decoder .......................................................................................................... 14
BER (Bit Error Rate)................................................................................................................................... 21
Chapter 4. IP Core Generation............................................................................................................. 22
Licensing the IP Core.......................................................................................................................................... 22
Getting Started .................................................................................................................................................... 22
IPexpress-Created Files and Top Level Directory Structure............................................................................... 25
Instantiating the Core .......................................................................................................................................... 26
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG32_02.7, June 2010
2
Block Viterbi Decoder User’s Guide
Lattice Semiconductor
Table of Contents
Enabling Hardware Evaluation in Diamond:............................................................................................... 27
Enabling Hardware Evaluation in ispLEVER:............................................................................................. 27
Updating/Regenerating the IP Core .................................................................................................................... 27
Regenerating an IP Core in Diamond ........................................................................................................ 27
Regenerating an IP Core in ispLEVER ...................................................................................................... 28
Chapter 5. Support Resources ............................................................................................................ 29
Telephone Support Hotline ........................................................................................................................ 29
E-mail Support ........................................................................................................................................... 29
Local Support ............................................................................................................................................. 29
Internet ....................................................................................................................................................... 29
Revision History .................................................................................................................................................. 30
Appendix A. Resource Utilization ....................................................................................................... 31
LatticeECP and LatticeEC FPGAs ...................................................................................................................... 31
Ordering Part Number................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 32
LatticeSC and LatticeSCM FPGAs ..................................................................................................................... 33
Ordering Part Number................................................................................................................................ 33
Ordering Part Number................................................................................................................................ 33
Ordering Part Number................................................................................................................................ 34
IPUG32_02.7, June 2010
3
Block Viterbi Decoder User’s Guide
Chapter 1:
Introduction
The Block Viterbi Decoder IP core is a parameterizable Viterbi Decoder for decoding different combinations of con-
volutionally encoded sequences. The decoder supports various code rates, constraint lengths, and generator poly-
nomials. It also allows soft-decision decoding and is capable of decoding punctured codes. The core can operate in
continuous or block modes, whichever is required by the channel. Either Tail Biting or Zero Flushing convolutional
codes can be decoded in the block mode. All the configurable parameters, including operation mode, generator
polynomials, punctured block size, and puncture pattern can be defined by the user to suit the needs of their appli-
cation. The code rate and puncture pattern can also be changed dynamically through input ports during the opera-
tion of the decoder. Lattice’s Block Viterbi Decoder IP is compatible with many networking and wireless standards
that use different methods of convolutional encoding at the encoder.
Quick Facts
Table 1-1
through
Table 1-4
give quick facts about the Block Viterbi Decoder IP core for LatticeEC™, Lat-
ticeECP™, LatticeECP2™, LatticeECP2M™, LatticeECP3™, LattticeSC™, LatticeSCM™, LatticeXP™, and
LatticeXP2™, devices.
Table 1-1. Block Viterbi Decoder IP Core for LatticeEC/ECP/XP Devices Quick Facts
Block Viterbi IP Configuration
IEEE
802.16
2004- SC
PHY
FPGA Families Supported
Core
Requirements
Minimal Device Needed
Targeted Device
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
2
250
LFEC1E
LFECP6E
LFXP3C
500
LFEC10E
LFECP10E
LFXP10C
9950
16
3200
IEEE 802.16-
2004-OFDM
PHY
(dynamic
puncturing)
LFEC3E
LFECP6E
LFXP3C
2750
4
1050
IEEE 802.16-
2004-OFDM
PHY (fixed
puncturing)
LFEC6E
LFECP6E
LFXP6C
3300
4
1200
3GPP
DVB-S
IEEE
802.11A
LFEC3E
LFECP6E
LFXP3C
2600
4
900
LatticeEC/ECP/XP
LFEC20E-5F672C/ LFECP20E-5F672C/ LFXP20E-5F256C
Diamond
®
1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify
®
Pro for Lattice D-2009.12L-1
Aldec
®
Active-HDL
®
8.2 Lattice Edition
Mentor Graphics
®
ModelSim
®
SE 6.3F
IPUG32_02.7, June 2010
4
Block Viterbi Decoder User’s Guide
Lattice Semiconductor
Introduction
Table 1-2. Block Viterbi Decoder IP Core for LatticeECP2/ECP2M/XP2 Devices Quick Facts
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FPGA/CPLD
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