5T93GL06NLGI datasheet, PDF - EEWORLD Datasheet

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5T93GL06NLGI: Descriptionclock buffer 2.5V lvds 1:6 clock buffer; Categorysemiconductor Other integrated circuit (IC); File Size401KB，18 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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5T93GL06NLGI Overview

clock buffer 2.5V lvds 1:6 clock buffer

5T93GL06NLGI Parametric

Parameter Name	Attribute value
Manufacture	IDT (Integrated Device Technology)
Product Category	Clock Buffe
RoHS	Yes
Package / Case	VFQFPN-28
Packaging	Tube
Factory Pack Quantity	245

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2.5V LVDS, 1:6 Glitchless Clock Buffer

TERABUFFER™ II

General Description

The IDT5T93GL06 2.5V differential clock buffer is a user- selectable

differential input to six LVDS outputs. The fanout from a differential

input to six LVDS outputs reduces loading on the preceding driver

and provides an efficient clock distribution network. The

IDT5T93GL06 can act as a translator from a differential HSTL,

eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to

LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be

used to translate to LVDS outputs. The redundant input capability

allows for a glitchless change-over from a primary clock source to a

secondary clock source up to 650MHz. Selectable inputs are

controlled by SEL. During the switchover, the output will disable low

for up to three clock cycles of the previously-selected input clock.

The outputs will remain low for up to three clock cycles of the

newly-selected clock, after which the outputs will start from the

newly-selected input. A FSEL pin has been implemented to control

the switchover in cases where a clock source is absent or is driven to

DC levels below the minimum specifications.

The IDT5T93GL06 outputs can be asynchronously enabled/

disabled. When disabled, the outputs will drive to the value selected

by the GL pin. Multiple power and grounds reduce noise.

IDT5T93GL06

NRND

DATA SHEET

Features

•

Guaranteed low skew: <40ps (maximum)

Very low duty cycle distortion: <100ps (maximum)

High speed propagation delay: <2ns (maximum)

Up to 800MHz operation

Glitchless input clock switching up to 650MHz

Selectable inputs

Hot insertable and over-voltage tolerant inputs

3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL

(3.3V), CML or LVDS input interface

Selectable differential inputs to six LVDS outputs

Power-down mode

At power-up, FSEL should be LOW

2.5V V

-40°C to 85°C ambient operating temperature

Available in VFQFN package

Recommends IDT5T9306 if glitchless input selection is not

required

Not Recommended for New Designs

Applications

•

Clock distribution

Pin Assignment

28 27 26 25 24 23 22

FSEL

SEL

GND

10 11 12 13 14

28-Lead VFQFN

4.8mm x 4.8mm x 0.925mm package body

K Package

Top View

IDT5T93GL06 REVISION C JANUARY 18, 2013

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