AS4C32M16D2
512M (32M x 16 bit) DDRII Synchronous DRAM (SDRAM)
Confidential
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: V
DD
& V
DDQ
= +1.8V
0.1V
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 400 MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
-DQS & DQS#
4 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
WRITE latency = READ latency - 1 t
CK
Burst lengths: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
Off-Chip Driver (OCD)
-Impedance Adjustment
-Adjustable data-output drive strength
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
Operating temperature range
-
Commercial (-0 ~
85°C)
- Industrial (-40 ~
95°C)
8192 refresh cycles / 64ms
- Average refresh period
7.8µs @ 0℃
≦TC≦
+85℃
3.9µs @ +85℃
＜TC≦
+95℃
Advanced (Rev. 1.1, Feb. /2013)
Overview
The AS4C32M16D2 DDR2 SDRAM is a high-speed CMOS
Double-Data-Rate-Two (DDR2), synchronous dynamic
random-access memory (SDRAM) containing 512 Mbits in
a 16-bit wide data I/Os. It is internally configured as a quad
bank DRAM, 4 banks x 8Mb addresses x 16 I/Os
The device is designed to comply with DDR2 DRAM key
features such as posted CAS# with additive latency, Write
latency = Read latency -1, Off-Chip Driver (OCD) impedance
adjustment, and On Die Termination(ODT)
.
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks. Inputs
are latched at the cross point of differential clocks (CK
rising and CK# falling)
All I/Os are synchronized with a pair of bidirectional
strobes (DQS and DQS#) in a source synchronous fashion.
The address bus is used to convey row, column, and bank
address information in RAS #
, CAS# multiplexing style. Accesses begin with the
registration of a Bank Activate command, and then it is
followed by a Read or Write command. Read and write
accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Operating the four memory banks in an
interleaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the
end of the burst sequence. A sequential and gapless data
rate is possible depending on burst length, CAS latency,
and speed grade of the device.
84-ball 8x12.5x1.2mm (max) FBGA
-
Pb and Halogen Free
Ordering Information
Part Number
AS4C32M16D2-25BCN
AS4C32M16D2-25BIN
Clock Frequency
400MHz
400MHz
Data Rate
800Mbps/pin
800Mbps/pin
Package
84-ball FBGA
84-ball FBGA
Temperature
Commercial
Industrial
Temp Range
-0° ~
85°C
-40° ~
95°C
B: indicates 84-ball (8.0 x 12.5 x 1.2mm) TFBGA package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates Pb and Halogen Free ROHS
Alliance Memory Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
1
Rev. 1.1
Feb. /2013
AS4C32M16D2
Figure 1. Ball Assignment (FBGA Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VDD
VSS
NC
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
2
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
3
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE#
BA1
A1
A5
A9
NC
…
7
VSSQ
UDQS
.
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
NC
8
UDQS#
VSSQ
DQ8
VSSQ
LDQS#
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
NC
9
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
Alliance Memory Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
2
Rev. 1.1
Feb. /2013
AS4C32M16D2
Figure 2. Block Diagram
CK
CK#
CKE
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
DLL
CLOCK
BUFFER
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
8M x 16
CELL ARRAY
(BANK #0)
Column Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
8M x 16
CELL ARRAY
(BANK #1)
Column Decoder
A0
A9
A11
A12
BA0
BA1
~
ADDRESS
BUFFER
8M x 16
CELL ARRAY
(BANK #2)
Column Decoder
REFRESH
COUNTER
LDQS
LDQS#
UDQS
UDQS#
DATA
STROBE
BUFFER
DQ0
DQ15
~
DQ
Buffer
8M x 16
CELL ARRAY
(BANK #3)
Column Decoder
ODT LDM
UDM
Alliance Memory Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
3
Rev. 1.1
Feb. /2013
AS4C32M16D2
Figure 3. State Diagram
CKEL
Initialization
Sequence
PR
Setting
MR,
EMR(1)
EMR(2)
EMR(3)
Self
Refreshing
OCD
calibration
SR F
H
C KE
(E)MRS
Idle
All banks
precharged
REF
Refreshing
CK
ACT
CK
EL
Precharge
Power
Down
EH
CK
EL
Activating
CKEL
Active
Power
Down
C KE
L
CKEL
Automatic Sequence
Cammand Sequence
C KEH
C KE
L
WR
Bank
Active
RD
Reading
WR
Writing
RD
W
RA
WR
RD
RD
A
RDA
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down,exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
WRA
A
WR
PR, PRA
PR, PRA
Writing
With
Autoprecharge
RDA
PR, PRA
Reading
With
Autoprecharge
Precharging
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the
commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among
other things, are not captured in full detail.
Alliance Memory Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
4
Rev. 1.1
Feb. /2013
AS4C32M16D2
Ball Descriptions
Table 3. Ball Descriptions
Symbol
CK, CK#
Type
Input
Description
Differential Clock:
CK, CK# are driven by the system clock. All SDRAM input signals are
sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data
is referenced to the crossings of CK and CK# (both directions of crossing).
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes LOW
synchronously with clock, the internal clock is suspended from the next clock cycle and the
state of output and burst address is frozen as long as the CKE remains LOW. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes.
Bank Address:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs:
A0-A12 are sampled during the BankActivate command (row address A0-A12)
and Read/Write command (column address A0-A9 with A10 defining Auto Precharge).
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder.
All commands are masked when CS# is sampled HIGH. CS# provides for external bank
selection on systems with multiple banks. It is considered part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction with
the CAS# and WE# signals and is latched at the crossing of positive edges of CK and negative
edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the WE# signal. When the
WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by
BA is turned on to the active state. When the WE# is asserted "LOW," the Precharge
command is selected and the bank designated by BA is switched to the idle state after the
precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction
with the RAS# and WE# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by
asserting WE# “HIGH " or “LOW".
Write Enable:
The WE# signal defines the operation commands in conjunction with the RAS#
and CAS# signals and is latched at the crossing of positive edges of CK and negative edge of
CK#. The WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
Bidirectional Data Strobe:
Specifies timing for Input and Output data. Read Data Strobe is
edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is
for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS may be used in single
ended mode or paired with LDQS# and UDQS# to provide differential pair signaling to the
system during both reads and writes. A control bit at EMR (1)[A10] enables or disables all
complementary data strobe signals.
Data Input Mask:
Input data is masked when DM is sampled HIGH during a write cycle. LDM
masks DQ0-DQ7, UDM masks DQ8-DQ15.
CKE
Input
BA0, BA1
A0-A12
CS#
Input
Input
Input
RAS#
Input
CAS#
Input
WE#
Input
LDQS,
LDQS#
UDQS
UDQS#
LDM,
UDM
Input /
Output
Input
Alliance Memory Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
5
Rev. 1.1
Feb. /2013
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