74AHCT373D,112 datasheet, PDF - EEWORLD Datasheet

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74AHCT373D,112: Descriptionlatches octal 3-state latch; Categorylogic logic; File Size93KB，18 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74AHCT373D,112 Overview

latches octal 3-state latch

74AHCT373D,112 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconduc
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOP
package instruction	SOP, SOP20,.4
Contacts	20
Manufacturer packaging code	SOT163-1
Reach Compliance Code	compli
series	AHCT/VHCT
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	12.8 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Su	17 ns
propagation delay (tpd)	17 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm

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74AHC373; 74AHCT373

Octal D-type transparant latch; 3-state

Rev. 03 — 20 May 2008

Product data sheet

1. General description

The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC373; 74AHCT373 consists of eight D-type transparent latches featuring

separate D-type inputs for each latch and 3-state true outputs for bus oriented

applications. A latch enable input (LE) and an output enable input (OE) are common to all

latches.

When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the

latches are transparent, i.e. a latch output will change state each time its corresponding

Dn input changes. When pin LE is LOW, the latches store the information that is present

at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.

When pin OE is LOW, the contents of the 8 latches are available at the outputs. When

pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE

input does not affect the state of the latches.

The 74AHC373; 74AHCT373 is functionally identical to the 74AHC573; 74AHCT573, but

has a different pin arrangement.

2. Features

Balanced propagation delays

All inputs have a Schmitt-trigger action

Common 3-state output enable input

Inputs accepts voltages higher than V

Functionally identical to the 74AHC573; 74AHCT573

Input levels:

For 74AHC373: CMOS input level

For 74AHCT373: TTL input level

ESD protection:

HBM EIA/JESD22-A114E exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101C exceeds 1000 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

74AHCT373D,112 Related Products

	74AHCT373D,112	74AHC373D,118	74AHC373D,112	74AHC373PW,112
Description	latches octal 3-state latch	latches octal 3-state latch	latches octal 3-state latch	latches octal 3-state latch
Brand Name	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP
Parts packaging code	SOP	SOP	SOP	TSSOP2
package instruction	SOP, SOP20,.4	7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20	7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20	TSSOP, TSSOP20,.25
Contacts	20	20	20	20
Manufacturer packaging code	SOT163-1	SOT163-1	SOT163-1	SOT360-1
Reach Compliance Code	compli	compli	compli	compli
series	AHCT/VHCT	AHC	AHC	AHC
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e4	e4	e4	e4
length	12.8 mm	12.8 mm	12.8 mm	6.5 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
MaximumI(ol)	0.008 A	0.008 A	0.008 A	0.008 A
Humidity sensitivity level	1	1	1	1
Number of digits	8	8	8	8
Number of functions	1	1	1	1
Number of ports	2	2	2	2
Number of terminals	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	TSSOP
Encapsulate equivalent code	SOP20,.4	SOP20,.4	SOP20,.4	TSSOP20,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TUBE	TAPE AND REEL	TUBE	TUBE
Peak Reflow Temperature (Celsius)	260	260	260	260
power supply	5 V	2/5.5 V	2/5.5 V	2/5.5 V
Prop。Delay @ Nom-Su	17 ns	11.5 ns	11.5 ns	11.5 ns
propagation delay (tpd)	17 ns	18.5 ns	18.5 ns	18.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.65 mm	2.65 mm	2.65 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30
width	7.5 mm	7.5 mm	7.5 mm	4.4 mm

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