74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Rev. 03 — 20 May 2008
Product data sheet
1. General description
The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC373; 74AHCT373 consists of eight D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications. A latch enable input (LE) and an output enable input (OE) are common to all
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The 74AHC373; 74AHCT373 is functionally identical to the 74AHC573; 74AHCT573, but
has a different pin arrangement.
2. Features
I
I
I
I
I
I
Balanced propagation delays
All inputs have a Schmitt-trigger action
Common 3-state output enable input
Inputs accepts voltages higher than V
CC
Functionally identical to the 74AHC573; 74AHCT573
Input levels:
N
For 74AHC373: CMOS input level
N
For 74AHCT373: TTL input level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC373
74AHC373D
74AHC373PW
74AHCT373
74AHCT373D
74AHCT373PW
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
Name
Description
Version
Type number
4. Functional diagram
3
4
7
8
13
14
17
18
11
1
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
LATCH
1 TO 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae050
Fig 1.
Functional diagram
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
2 of 17
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
5. Pinning information
5.1 Pinning
74AHC373
74AHCT373
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
001aai132
GND 10
Fig 6.
Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
LE
Q4
D4
D5
Q5
Q6
D6
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Description
3-state output enable input (active LOW)
3-state latch output
data input
data input
3-state latch output
3-state latch output
data input
data input
3-state latch output
ground (0 V)
latch enable input (active HIGH)
3-state latch output
data input
data input
3-state latch output
3-state latch output
data input
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
4 of 17
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Table 2.
Symbol
D7
Q7
V
CC
Pin description
…continued
Pin
18
19
20
Description
data input
3-state latch output
supply voltage
6. Functional description
Table 3.
Function table
[1]
Control
OE
Enable and read register (transparent mode)
Latch and read register
Latch register and disable outputs
L
L
H
LE
H
L
X
Input
Dn
L
H
l
h
X
X
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
Operating mode
Internal
latch
L
H
L
H
X
X
Output
Q0 to Q7
L
H
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
74AHC_AHCT373_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
5 of 17
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
