2.5V LVDS, 1:2 Clock Buffer Terabuffer™II
IDT5T9302I
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPEMBER 7, 2016
DATA SHEET
General Description
The IDT5T9302I 2.5V differential clock buffer is a user-selectable
differential input to two LVDS outputs. The fanout from a differential
input to two LVDS outputs reduces loading on the preceding driver
and provides an efficient clock distribution network. The IDT5T9302I
can act as a translator from a differential HSTL, eHSTL, LVEPECL
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A
single-ended 3.3V / 2.5V LVTTL input can also be used to translate
to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a
secondary clock source. Selectable reference inputs are controlled
by SEL.
The IDT5T9302I outputs can be asynchronously enabled/ disabled.
When disabled, the outputs will drive to the value selected by the GL
pin. Multiple power and grounds reduce noise.
Features
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Guaranteed low skew: 50ps (maximum)
Very low duty cycle distortion: 125ps (maximum)
High speed propagation delay: 1.5ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to two LVDS outputs
Power-down mode
2.5V V
DD
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Not Recommended For New Designs
For functional replacement part use 8SLVP1102
Applications
•
Clock distribution
Pin Assignment
GND
nPD
nc
V
DD
nQ1
Q1
V
DD
SEL
nG
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A2
nA2
GND
V
DD
nQ2
Q2
V
DD
GL
nA1
A1
Block Diagram
GL
nG
IDT5T9302I
20-Lead TSSOP, E-Pad
4.4mm x 6.5mm x 0.925mm
package body
Q1
G Package
Top View
nQ1
OUTPUT
CONTROL
nPD
A1
nA1
1
OUTPUT
CONTROL
Q2
nQ2
A2
nA2
0
SEL
5T9302 Rev A 12/16/14
1
©2014 Integrated Device Technology, Inc.
5T9302 DATA SHEET
Table 1. Pin Descriptions
Name
A[1:2]
Input
Type
Adjustable
(1, 4)
Adjustable
(1, 4)
Description
Clock input. A
[1:2]
is the "true" side of the differential clock input.
Complementary clock inputs. nA[1:2] is the complementary side of A[1:2]
.
For LVTTL
single-ended operation, nA[1:2]should be set to the desired toggle voltage for A[1:2]:
3.3V LVTTL V
REF
= 1650mV
2.5V LVTTL V
REF
= 1250mV
Gate control for differential outputs Q1, nQ1 and Q2, nQ2. When nG is LOW, the differential
outputs are active. When nG is HIGH, the differential outputs are asynchronously driven to
the level designated by GL
(2)
. See Table 3A.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"
outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs
disable HIGH. See Table 3A.
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and nA2. When HIGH, selects A1 and nA1.
See Table 3B.
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode.
Inputs and outputs are disabled. Both "true" and “complementary” outputs will pull to V
DD
.
Set HIGH for normal operation.
(3)
Power supply for the device core and inputs.
Power supply return for all power.
No connect; recommended to connect to GND.
nA[1:2]
Input
nG
Input
LVTTL
GL
Q[1:2]
nQ[1:2]
SEL
Input
Output
Output
Input
LVTTL
LVDS
LVDS
LVTTL
nPD
V
DD
GND
nc
Input
LVTTL
Power
Power
Unused
NOTES:
1.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting nPD.
4.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
3
Maximum
Units
pF
NOTE: This parameter is measured at characterization but not tested.
Rev A 12/16/14
2
2.5V LVDS, 1:2 CLOCK BUFFER TERABUFFER™II
5T9302 DATA SHEET
Function Tables
Table 3A. Gate Control Output Table
Control Output
GL
0
0
1
1
nG
0
1
0
1
Q[1:2]
Toggling
LOW
Toggling
HIGH
Outputs
nQ[1:2]
Toggling
HIGH
Toggling
LOW
Table 3B. Input Selection Table
Selection SEL pin
0
1
Inputs
A2, nA2
A1, nA1
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Power Supply Voltage, V
DD
Input Voltage, V
I
Output Voltage, V
O
Not to exceed 3.6V
Storage Temperature, T
STG
Junction Temperature, T
J
Rating
-0.5V to +3.6V
-0.5V to +3.6V
-0.5 to V
DD
+0.5V
-65C to 150C
150C
Recommended Operating Range
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Minimum
-40
2.3
Typical
+25
2.5
Maximum
+85
2.7
Units
C
V
2.5V LVDS, 1:2 CLOCK BUFFER TERABUFFER™II
3
Rev A 12/16/14
5T9302 DATA SHEET
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
DDQ
I
TOT
I
nPD
Parameter
Quiescent V
DD
Power Supply Current
Total Power V
DD
Supply Current
Total Power Down Supply Current
Test Conditions
V
DD
= Max.,
All Input Clocks = LOW
(2)
;
Outputs enabled
V
DD
= 2.7V;
F
REFERENCE
Clock = 450MHz
nPD = LOW
Minimum
Typical
(2)
Maximum
240
Units
mA
250
5
mA
mA
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2: The true input is held LOW and the complementary input is held HIGH.
Table 4B. LVCMOS/LVTTL DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
IK
V
IN
V
IH
V
IL
V
THI
V
REF
Parameter
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Input High Voltage
DC Input Low Voltage
DC Input Threshold Crossing Voltage
Single-Ended Reference Voltage
(3)
3.3V LVTTL
2.5V LVTTL
V
DD
/2
1.65
1.25
Test Conditions
V
DD
= = 2.7V
V
DD
= = 2.7V
V
DD
= 2.3V, I
IN
= -18mA
-0.3
1.7
0.7
-0.7
Minimum
Typical
(2)
Maximum
±5
±5
-1.2
3.6
Units
µA
µA
V
V
V
V
V
V
V
NOTE 1: See
Recommended Operating Range
table.
NOTE 2: Typical values are at V
DD
= 2.5V, +25°C ambient.
NOTE 3: For A[1:2] single-ended operation, nA[1:2] is tied to a DC reference voltage.
Table 4C. Differential DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
IK
V
IN
V
DIF
V
CM
Parameter
Input High Current
Input Low Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage
(3)
DC Common Mode Input Voltage
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
-0.3
0.1
0.05
V
DD
-0.7
Minimum
Typical
(2)
Maximum
±5
±5
-1.2
3.6
Units
µA
µA
V
V
V
V
NOTE 1: See
Recommended Operating Range
table.
NOTE 2: Typical values are at V
DD
= 2.5V, +25°C ambient.
NOTE 3: V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
NOTE 4: V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2.
Rev A 12/16/14
4
2.5V LVDS, 1:2 CLOCK BUFFER TERABUFFER™II
5T9302 DATA SHEET
Table 4D. LVDS DC Characteristics
(1)
,
T
A
= -40°C to 85°C
Symbol
V
OT(+)
V
OT(–)
V
OT
V
OS
V
OS
I
OS
I
OSD
Parameter
Differential Output Voltage for the
True Binary State
Differential Output Voltage for the
False Binary State
Change in V
OT
Between Complementary
Output States
Output Common Mode Voltage
(Offset Voltage)
Change in V
OS
Between Complementary
Output States
Outputs Short Circuit Current
Differential Outputs Short Circuit Current
V
OUT+ and
V
OUT–
= 0V
V
OUT+
= V
OUT–
12
6
1.125
1.2
Test Conditions
Minimum
247
247
Typical
(2)
Maximum
454
454
50
1.375
50
24
12
Units
mV
mV
mV
V
mV
mA
mA
NOTE 1: See
Recommended Operating Range
table.
NOTE 2: Typical values are at V
DD
= 2.5V, +25°C ambient.
AC Electrical Characteristics
Table 5A. HSTL Differential Input AC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
DIF
V
X
D
H
V
THI
t
R
/ t
F
Parameter
Input Signal Swing
(1)
Differential Input Signal Crossing Point
(2)
Duty Cycle
Input Timing Measurement Reference Level
(3)
Input Signal Edge Rate
(4)
Value
1
750
50
Crossing Point
2
Units
V
mV
%
V
V/ns
NOTE 1: The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the V
DIF
(AC) specification under actual use conditions.
NOTE 2: A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the V
X
specification under actual use conditions.
NOTE 3: In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4: The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
2.5V LVDS, 1:2 CLOCK BUFFER TERABUFFER™II
5
Rev A 12/16/14
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