74LV165
8-bit parallel-in/serial-out shift register
Rev. 7 — 9 March 2016
Product data sheet
1. General description
The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial
outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is
LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.
When input PL is HIGH, data enters the register serially at the input DS. It shifts one place
to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the
succeeding stage.
The clock input is a gate-OR structure which allows one input to be used as an active
LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is
arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the
input CE should only take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the
data when PL is activated.
2. Features and benefits
Wide supply voltage range from 1.0 V to 5.5 V
Synchronous parallel-to-serial applications
Optimized for low voltage applications: 1.0 V to 3.6 V
Synchronous serial input for easy expansion
Latch-up performance exceeds 250 mA
5.5 V tolerant inputs/outputs
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
JESD8-1A (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114-A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
3. Ordering information
Table 1.
Ordering information
Temperature range Name
74LV165D
74LV165DB
74LV165PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO16
SSOP16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number Package
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LV165
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 9 March 2016
2 of 20
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
Fig 4.
Logic diagram
74LV165
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 9 March 2016
3 of 20
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16 and (T)SSOP16
5.2 Pin description
Table 2.
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
CC
Pin description
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
Description
parallel enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary serial output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs
clock enable input (active LOW)
positive supply voltage
74LV165
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 9 March 2016
4 of 20
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
6. Functional description
Table 3.
Function table
[1]
Inputs
PL
parallel load
serial shift
hold “do nothing”
[1]
Operating modes
Qn registers
CE
X
X
L
L
H
CP
X
X
X
DS
X
X
l
h
X
D0 to D7
L
H
X
X
X
Q0
L
H
L
H
q0
Q1 to Q6
L to L
H to H
q0 to q5
q0 to q5
q1 to q6
Output
Q7
L
H
q6
q6
q7
Q7
H
L
q6
q6
q7
L
L
H
H
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Fig 6.
Timing diagram
74LV165
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 7 — 9 March 2016
5 of 20
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