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74LV165D-Q100J

Description
counter shift registers 8bit serial-in parallel-out
Categorysemiconductor    Other integrated circuit (IC)   
File Size796KB,20 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance  
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74LV165D-Q100J Overview

counter shift registers 8bit serial-in parallel-out

74LV165D-Q100J Parametric

Parameter NameAttribute value
ManufactureNXP
Product CategoryCounter Shift Registers
RoHSYes
Counting SequenceParallel to Serial
Number of Circuits8
Package / CaseSO-16
Logic Family74LV
Logic TypeTTL
Number of Input Lines8
Output TypeSerial
Propagation Delay Time18 ns
Maximum Operating Temperature+ 125 C
Minimum Operating Temperature- 40 C
PackagingReel
Functi8 Bit Parallel In Serial Out Shift Registe
Input TypeParallel
Mounting StyleSMD/SMT
Number of Output Lines8
Operating Supply Voltage3.3 V
ProducDriver ICs - Various
Factory Pack Quantity2500
Supply Voltage - Max5.5 V
Supply Voltage - Mi1 V
74LV165
8-bit parallel-in/serial-out shift register
Rev. 7 — 9 March 2016
Product data sheet
1. General description
The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial
outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is
LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.
When input PL is HIGH, data enters the register serially at the input DS. It shifts one place
to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the
succeeding stage.
The clock input is a gate-OR structure which allows one input to be used as an active
LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is
arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the
input CE should only take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the
data when PL is activated.
2. Features and benefits
Wide supply voltage range from 1.0 V to 5.5 V
Synchronous parallel-to-serial applications
Optimized for low voltage applications: 1.0 V to 3.6 V
Synchronous serial input for easy expansion
Latch-up performance exceeds 250 mA
5.5 V tolerant inputs/outputs
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
JESD8-1A (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114-A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C

74LV165D-Q100J Related Products

74LV165D-Q100J 74LV165DB,112 74LV165PW-Q100J 74LV165DB,118 74LV165PW,112 74LV165D,118
Description counter shift registers 8bit serial-in parallel-out counter shift registers 3.3V parallel load counter shift registers 8bit serial-in parallel-out counter shift registers 3.3V parallel load counter shift registers prllel-load 8bit S/R counter shift registers 3.3V parallel load
Brand Name - NXP Semiconduc NXP Semiconduc NXP Semiconduc NXP Semiconduc NXP Semiconductor
Is it Rohs certified? - conform to - conform to conform to conform to
Maker - NXP NXP NXP NXP NXP
Parts packaging code - SSOP1 TSSOP SSOP1 TSSOP SOP
package instruction - SSOP, SSOP16,.3 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 SSOP, TSSOP, TSSOP16,.25 -
Contacts - 16 16 16 16 16
Manufacturer packaging code - SOT338-1 SOT403-1 SOT338-1 SOT403-1 SOT109-1
Reach Compliance Code - compli unknow compli compli compliant
Other features - CLOCK INHIBIT - CLOCK INHIBIT CLOCK INHIBIT CLOCK INHIBIT
Counting direction - RIGHT - RIGHT RIGHT RIGHT
series - LV/LV-A/LVX/H - LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code - R-PDSO-G16 - R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code - e4 - e4 e4 e4
length - 6.2 mm - 6.2 mm 5 mm 9.9 mm
Load capacitance (CL) - 50 pF - 50 pF 50 pF 50 pF
Logic integrated circuit type - PARALLEL IN SERIAL OUT - PARALLEL IN SERIAL OUT PARALLEL IN SERIAL OUT PARALLEL IN SERIAL OUT
Humidity sensitivity level - 1 - 1 1 1
Number of digits - 8 - 8 8 8
Number of functions - 1 - 1 1 1
Number of terminals - 16 - 16 16 16
Maximum operating temperature - 125 °C - 125 °C 125 °C 125 °C
Minimum operating temperature - -40 °C - -40 °C -40 °C -40 °C
Output polarity - COMPLEMENTARY - COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material - PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - SSOP - SSOP TSSOP SOP
Package shape - RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR
Package form - SMALL OUTLINE, SHRINK PITCH - SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) - 260 - 260 260 260
propagation delay (tpd) - 90 ns - 90 ns 90 ns 90 ns
Certification status - Not Qualified - Not Qualified Not Qualified Not Qualified
Maximum seat height - 2 mm - 2 mm 1.1 mm 1.75 mm
Maximum supply voltage (Vsup) - 5.5 V - 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) - 1 V - 1 V 1 V 1 V
Nominal supply voltage (Vsup) - 3.3 V - 3.3 V 3.3 V 3.3 V
surface mount - YES - YES YES YES
technology - CMOS - CMOS CMOS CMOS
Temperature level - AUTOMOTIVE - AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface - NICKEL PALLADIUM GOLD - Nickel/Palladium/Gold (Ni/Pd/Au) NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD
Terminal form - GULL WING - GULL WING GULL WING GULL WING
Terminal pitch - 0.65 mm - 0.65 mm 0.65 mm 1.27 mm
Terminal location - DUAL - DUAL DUAL DUAL
Maximum time at peak reflow temperature - 30 - 30 30 30
Trigger type - POSITIVE EDGE - POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width - 5.3 mm - 5.3 mm 4.4 mm 3.9 mm
minfmax - 78 MHz - 78 MHz 78 MHz 78 MHz
Base Number Matches - 1 1 1 1 1
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