time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION, Rev. 00C
01/20/05
1
IS42S81600A, IS42S16800A, IS42S32400A
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
DD
and 3.3V V
DDQ
memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 512 columns by 16 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
ISSI
®
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
16
2
MODE
REGISTER
12
REFRESH
CONTROLLER
I/O 0-15
SELF
REFRESH
CONTROLLER
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
DATA OUT
BUFFER
16
16
V
DD
/V
DDQ
V
ss
/V
ss
Q
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
MEMORY CELL
ARRAY
12
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
®
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
I/O0
V
DD
Q
NC
I/O1
V
SS
Q
NC
I/O2
V
DD
Q
NC
I/O3
V
SS
Q
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O7
V
SS
Q
NC
I/O6
V
DD
Q
NC
I/O5
V
SS
Q
NC
I/O4
V
DD
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A9
BA0, BA1
I/O0 to I/O7
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x 8 Lower Byte, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
01/20/05
3
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
®
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
I/O0
V
DD
Q
I/O1
I/O2
V
SS
Q
I/O3
I/O4
V
DD
Q
I/O5
I/O6
V
SS
Q
I/O7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O15
V
SS
Q
I/O14
I/O13
V
DD
Q
I/O12
I/O11
V
SS
Q
I/O10
I/O9
V
DD
Q
I/O8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQML
DQMH
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
I/O15
V
SS
Q
I/O14
I/O13
V
DD
Q
I/O12
I/O11
V
SS
Q
I/O10
I/O9
V
DD
Q
I/O8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
I/O31
V
DD
Q
I/O30
I/O29
V
SS
Q
I/O28
I/O27
V
DD
Q
I/O26
I/O25
V
SS
Q
I/O24
V
SS
®
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
I/O0
V
DD
Q
I/O1
I/O2
V
SS
Q
I/O3
I/O4
V
DD
Q
I/O5
I/O6
V
SS
Q
I/O7
NC
V
DD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
I/O16
V
SS
Q
I/O17
I/O18
V
DD
Q
I/O19
I/O20
V
SS
Q
I/O21
I/O22
V
DD
Q
I/O23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
I/O0 to I/O31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com —
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